Method and system for reducing write latency in a data storage system by using a command-push model

Patent metadata

Field	Value
Publication number	US-9256384-B2
Application number	US-201313758853-A
Country	US
Kind code	B2
Filing date	Feb 4, 2013
Priority date	Feb 4, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency.

First claim

What is claimed is:

1. A data storage system comprising:
a host system comprising a system processor and a system memory device;
a memory controller comprising a controller processor, a nonvolatile memory (NVM) device and an input/output (I/O) interface device, wherein a portion of the NVM device is used as a command queue;
at least one solid state drive (SSD) connected to the I/O interface device, wherein said at least one SSD is configured as an array of physical disk drives (PDs); and
a bus interconnecting the host system with the memory controller, wherein the host system accesses the NVM device via the bus and pushes commands into the command queue of the NVM device via the bus.

2. The data storage system of claim 1 , wherein the system processor executes a memory driver program that accesses the NVM device via the bus and pushes the commands into the command queue of the NVM device via the bus.

3. The data storage system of claim 1 , wherein the memory controller further comprises a direct memory access (DMA) engine that directly accesses the NVM device, and wherein the system processor executes a memory driver program that pushes the commands to the DMA engine via the bus, and wherein the DMA engine stores the commands in the command queue of the NVM device.

4. The data storage system of claim 1 , wherein the host system notifies the memory controller when a command has been pushed into the command queue of the NVM device.

5. The data storage system of claim 2 , wherein the host system and the NVM device use a same command and data structure.

6. The data storage system of claim 5 , wherein the bus is a peripheral interconnect express (PCIe) bus, and wherein the memory driver program accesses the NVM device by using base address registers (BARs) of the PCIe bus.

7. A memory controller comprising:
an input/output (I/O) interface device, wherein a portion of the NVM device is used as a command queue;
at least one solid state drive (SSD) connected to the I/O interface device, wherein said at least one SSD is configured as an array of physical disk drives (PDs);
a controller processor; and
a nonvolatile memory (NVM) device, a portion of the NVM device being allocated as a command queue, wherein the NVM device is configured to be accessed by a host system via a bus that interconnects the host system with the memory controller, wherein the NVM device is configured to allow the host system to push commands into the command queue of the NVM device via the bus.

8. The memory controller of claim 7 , wherein the NVM device is accessed by the host system via a memory driver program being executed by a processor of the host system, and wherein the bus is a peripheral interconnect express (PCIe) bus, and wherein the NVM device is accessible by the memory driver program through base address registers (BARs) of the PCIe bus.

9. The memory controller of claim 7 , wherein the memory controller further comprises:
a direct memory access (DMA) engine that communicates with the host system via the bus and that communicates directly with the NVM device, and wherein the DMA engine is accessed by the host system via the bus, and the DMA engine receives commands pushed to the DMA engine by the memory driver program and stores the commands in the command queue of the NVM device.

10. The memory controller of claim 8 , wherein the NVM device uses a same command and data structure as the host system.

11. A method for reducing latency in a data storage system, the method comprising:
in a memory controller comprising a controller processor, a nonvolatile memory (NVM) device and an input/output (I/O) interface device connected to at least one solid state drive (SSD) configured as an array of physical disk drives (PDs), configuring a portion of the NVM device as a command queue;
with a host system interconnected with the memory controller via a bus, pushing a command into the memory controller via the bus; and
in the memory controller, storing the command in the command queue of the NVM device.

12. The method of claim 11 , wherein a system processor of the host system executes a memory driver program that accesses the NVM device via the bus and pushes the commands into the command queue of the NVM device via the bus.

13. The method of claim 11 , wherein the memory controller further comprises a direct memory access (DMA) engine, and wherein a system processor of the host system executes a memory driver program that pushes commands from the host system to the DMA engine via the bus, and wherein the DMA engine stores the commands into the command queue of the NVM device via the bus.

14. The method of claim 12 , further comprising:
wherein the host system notifies the memory controller when a command has been pushed into the command queue of the NVM device.

15. The method of claim 12 , wherein the host system and the NVM device use a same command and data structure.

16. The method of claim 15 , wherein the bus is a peripheral interconnect express (PCIe) bus, and wherein the memory driver program accesses the NVM device by using base address registers (BARs) of the PCIe bus.

17. A non-transitory computer-readable medium having a computer program stored thereon for execution by a processor of a host system for pushing commands into a command queue of a non-volatile memory (NVM) device of a memory controller that is connected to the host system via a bus, the computer program comprising:
a first code portion for receiving a command to read or write one or more addresses of a solid state drive (SSD) configured as an array of physical disk drives (PDs); and
a second code portion for pushing the command into the memory controller.

18. The non-transitory computer-readable medium of claim 17 , wherein the second code portion pushes the command into the command queue of the NVM device, and wherein the computer program further comprises:
a third code portion for notifying a processor of the memory controller when the command has been pushed into the command queue of the NVM device of the memory controller.

19. The non-transitory computer-readable medium of claim 17 , wherein the second code portion pushes the command into a direct memory access (DMA) engine of the memory controller, wherein the DMA engine is directly connected to the NVM device to allow the DMA engine to store the command in the command queue, and wherein the computer program further comprises:
a third code portion for notifying a processor of the memory controller when the command has been pushed into the command queue of the NVM device of the memory controller.

Assignees

• Lsi Corp
• Avago Technologies General Ip

Inventors

• Bert Luca
• Baderdinni Anant
• Simionescu Horia
• Ish Mark

Classifications

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title