Method for measuring interface state density
US-9110126-B2 · Aug 18, 2015 · US
Testing structure and method for interface trap density of gate oxide
US9255960B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9255960-B2 |
| Application number | US-201314350442-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2013 |
| Priority date | Aug 29, 2012 |
| Publication date | Feb 9, 2016 |
| Grant date | Feb 9, 2016 |
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Abstract
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The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation.
First claim
Opening claim text (preview).
What is claimed is: 1. A testing structure for interface trap density of gate oxide layer, comprising a gate oxide layer testing portion of p-type MOS device and a gate oxide layer testing portion of n-type MOS device, wherein the two testing portions share a common gate. 2. The testing structure according to claim 1 , wherein the gate oxide layer testing portion of the p-type MOS device includes a gate oxide layer, a P-type emitter, and a P-type substrate of P…
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Electricity · mapped topic
Electricity · mapped topic
- G01R31/2621Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9255960B2 cover?
- The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half bu…
- Who is the assignee on this patent?
- Univ Beijing
- What technology area does this patent fall under?
- Primary CPC classification G01R31/2621. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).