Apparatus for testing electronic devices
US-2015369858-A1 · Dec 24, 2015 · US
Method for testing density and location of gate dielectric layer trap of semiconductor device
US9018968B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018968-B2 |
| Application number | US-201213879967-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 28, 2012 |
| Priority date | Jun 9, 2011 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Abstract
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Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for testing a trap density and a two-dimensional trap location in a gate dielectric layer of a semiconductor device, the method comprising: forming four lead-out terminals A 1 , A 2 , B 1 and B 2 in four different directions from a gate region of the semiconductor device, with an end of each of the four terminals connected to the gate region; with terminals A 1 and A 2 positioned along a channel direction, and with terminals B 1 and B 2 positi…
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Electricity · mapped topic
Electricity · mapped topic
- G01R31/2642Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9018968B2 cover?
- Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The presen…
- Who is the assignee on this patent?
- Huang Ru, Zou Jibin, Liu Changze, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification G01R31/2642. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).