Hardware-efficient signal-component separator for outphasing power amplifiers

Patent metadata

Field	Value
Publication number	US-9252712-B2
Application number	US-201314400061-A
Country	US
Kind code	B2
Filing date	May 10, 2013
Priority date	May 10, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Described herein is a fixed-point piece-wise linear (FP PWL) approximation technique for computations of nonlinear functions. The technique results in circuit designs having relatively few and simple arithmetic operations, short arithmetic operands and small-sized look-up tables and the circuits resultant there from can be efficiently pipelined to run at multi-GSamples/s throughputs. In one exemplary embodiment, the FP PWL approximation technique was used in the design of an energy-efficient high-throughput and high-precision signal component separator (SCS) for use with in an asymmetric-multilevel-outphasing (AMO) power amplifier. The FP PWL approximation technique is appropriate for use in any application requiring high-throughput, area and power constrained hardware implementations of nonlinear functions.

First claim

The invention claimed is:

1. A circuit to implement a nonlinear function designed by representing the nonlinear function as a fixed point piece-wise linear (PWL) approximation, the circuit comprising:
a look up table (LUT) stored in a memory of the circuit, the LUT configured to receive m 1 most significant bits (MSBs) and m 2 least significant bits (LSBs) of an input as an address and for providing parameters b i , k i , S i of a corresponding interval of the nonlinear function at an output thereof, where b i is a first fixed point value, S i is a second fixed point value, and k i is a third fixed point value, and where k i corresponds to a slope value of the nonlinear function in the corresponding interval;
a multiplier of the circuit; and
an adder of the circuit, said lookup table, said multiplier and said adder configured to implement the nonlinear function by representing the nonlinear function as a fixed point piece-wise linear (PWL) approximation, y i , computed as:

y
1

=

b
i

·
1

︸

m
1

-
MSBbit

+

k
i

⁡

(

x
2

-

S
i

·
1

)

︸

m
2

-
LSBbit

,

i
=
0

,
1
,

…
⁢

⁢

2

m
1

-
1

,

in which:

y
i

=

[

y
⁡

(

[

i
,
0

]

)

,

y
⁡

(

[

i
,
1

]

)

,
…
⁢

,

y
⁡

(

[

i
,

N
2

-
1

]

)

]

T

x
2

=

1
N

⁡

[

0
,
1
,
…
⁢

,

N
2

-
1

]

T

1
=

[

1
,
1
,
…
⁢

,
1

]

T

∈

ℝ

N
2

N
1

=

2

m
1

N
2

=

2

m
2

Assignees

• Li Yan
• Li Zhipeng
• Avniel Yehuda
• Megretski Alexandre
• Stojanovic Vladimir Marko
• Massachusetts Inst Technology

Inventors

• Li Yan
• Li Zhipeng
• Avniel Yehuda
• Megretski Alexandre
• Stojanovic Vladimir Marko

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F1/0205 Primary

  in transistor amplifiers · CPC title

• H03F1/0294 Primary

  using vector summing of two or more constant amplitude phase-modulated signals · CPC title

• H04L25/03

  Shaping networks in transmitter or receiver, e.g. adaptive shaping networks · CPC title

• H03F3/245

  with semiconductor devices only · CPC title