Three dimensional integrated circuit electrostatic discharge protection and prevention test interface

Patent metadata

Field	Value
Publication number	US-9252593-B2
Application number	US-201213716272-A
Country	US
Kind code	B2
Filing date	Dec 17, 2012
Priority date	Dec 17, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.

First claim

We claim:

1. A method of providing electrostatic discharge protection comprising the steps of:
(a) providing a probe card assembly electrically connected to a plurality of input/output (I/O) channels;
(b) contacting the probe card assembly with a secondary assembly, the secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test, the one or more wafers having charges thereon;
(c) forcing a first voltage on ones of the plurality of I/O channels of the probe card assembly, so as to program I/O levels of the device under test to the first voltage; and
(d) after step (c), forcing a second voltage of same magnitude and opposite sign from the first voltage on the ones of the plurality of I/O channels of the probe card assembly, so as to program the I/O levels of the device under test to the second voltage, to dissipate the charges.

2. The method of claim 1 wherein steps (a)-(c) are performed before testing of the wafer.

3. The method of claim 1 wherein the forced voltage is positive and the dissipated charges are negative.

4. The method of claim 1 wherein the forced voltage is negative and the dissipated charges are positive.

5. The method of claim 1 wherein the step of contacting the probe card assembly with the secondary assembly further comprises contacting ones of a plurality of probe card pins in the probe card assembly to probe pads on the one or more wafers to connect to the wafer to an input/output ground channel having a resistance to dissipate charges on the wafer.

6. The method of claim 1 wherein the step of contacting the probe card assembly with the secondary assembly further comprises contacting ones of a plurality of probe card pins in the probe card assembly to probe pads on the one or more wafers to connect to the wafer to an input/output power channel having a resistance to dissipate charges on the wafer.

7. The method of claim 1 wherein step (c) comprises programming levels of ones of the plurality of input/output channels to a first program voltage at a first waiting time and then step (d) comprises programming the levels of the ones of the plurality of input/output channels to a second program voltage opposite the first program voltage at the first waiting time to dissipate charges on the wafer.

8. The method of claim 1 , wherein a parametric measurement unit forces the voltages on the plurality of input/output channels.

9. The method of claim 1 , wherein step (c) includes executing instructions within a pattern generator in a host computer to produce a sequence of data values providing channel instructions.

10. The method of claim 1 , wherein the secondary assembly further comprises an array of control collapse chip connection bumps connected to respective through silicon vias which are electrically connected to an array of microbumps, the microbumps adaptable to provide an electrical connection between the probe card assembly and the devices under test.

11. A method of providing electrostatic discharge protection comprising the steps of:
(a) providing a probe card assembly electrically connected to a plurality of input/output (I/O) channels;
(b) contacting the probe card assembly with a secondary assembly, the secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test, the one or more wafers having charges thereon; and
(c) programming a first predetermined voltage on ones of the plurality of I/O channels of the probe card assembly; and
(d) after step (c), programming a second predetermined voltage opposite the first predetermined voltage on the ones of the plurality of I/O channels of the probe card assembly, to dissipate a charge from the wafer; and
(e) performing a wafer level test on the device under test after completing step (c).

12. The method of claim 11 , wherein step (c) includes performing a PMU discharge process for programming all I/O pin levels to the first predetermined voltage.

13. The method of claim 12 , wherein step (d) comprises programming all I/O pin levels to the second predetermined voltage.

14. The method of claim 11 wherein the step of contacting the probe card assembly with the secondary assembly further comprises contacting ones of a plurality of probe card pins in the probe card assembly to probe pads on the one or more wafers to connect to the wafer to an input/output ground channel having a resistance to dissipate charges on the wafer.

15. The method of claim 11 wherein the step of contacting the probe card assembly with the secondary assembly further comprises contacting ones of a plurality of probe card pins in the probe card assembly to probe pads on the one or more wafers to connect to the wafer to an input/output power channel having a resistance to dissipate charges on the wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Mill-Jer
• Peng Ching-Nen
• Lin Hung-Chih
• Chen Hao

Classifications

• G01R1/36

  Overload-protection arrangements or circuits for electric measuring instruments · CPC title

• H05K2201/10734

  Ball grid array [BGA]; Bump grid array · CPC title

• G01R1/07378

  using an intermediate adapter, e.g. space transformers (G01R1/07371 takes precedence) · CPC title

• H05F3/02 Primary

  by means of earthing connections · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title