Non-planar gate all-around device and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9252275-B2
Application number	US-201414582131-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising a first material, the first material having a first lattice constant;
a source region above the substrate, the source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;
a drain region above the substrate, the drain region comprising the second material;
a first nanowire, the first nanowire being coupled to the source region and being coupled to the drain region, the first nanowire comprising a third material, the third material having a third lattice constant substantially the same as the second lattice constant;
a second nanowire above the first nanowire and not in direct contact with the first nanowire, the second nanowire being coupled to the source region and being coupled to the drain region, the second nanowire comprising the third material;
a gate dielectric layer around at least a portion of the first nanowire and around at least a portion of the second nanowire; and
a gate electrode around at least a portion of the first nanowire and around at least a portion of the second nanowire, the gate electrode being separated from the first and second nanowires by at least the gate dielectric layer.

2. The device of claim 1 , wherein the second lattice constant is larger than the first lattice constant.

3. The device of claim 1 , wherein the second material is the same as the third material.

4. The device of claim 1 , wherein the source region and the drain region both have side walls that are angled.

5. The device of claim 1 , wherein the source region has a first width at a first position above the substrate, the source region has a second width at a second position above the substrate, the second position being a different distance from the substrate than the first position, and the first width is greater than the second width.

6. The device of claim 5 , wherein the first width of the source is greater than a maximum width of the first nanowire.

7. The device of claim 1 , further comprising an isolation region layer over a first portion of the substrate, wherein a second portion of the substrate extends up past a bottom surface of the isolation region layer.

8. The device of claim 7 , wherein the second portion of the substrate does not extend up to a top surface of the isolation region layer.

9. The device of claim 7 , wherein at least portions of the first and second nanowires are directly above the second portion of the substrate, but are not in direct contact with the second portion of the substrate.

10. The device of claim 1 , wherein the drain region has a side wall, the side wall of the drain region is a <111> facet.

11. A semiconductor device, comprising:
a semiconductor substrate comprising a first semiconductor material, the semiconductor substrate having a top surface, wherein the first semiconductor material of the semiconductor substrate adjacent the top surface has a first lattice constant;
an epitaxial source region on the top surface of the semiconductor substrate, the epitaxial source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;
an epitaxial drain region on the top surface of the semiconductor substrate, the epitaxial drain region comprising the second material with the second lattice constant different than the first lattice constant, the epitaxial drain region being spaced apart from the epitaxial source region;
a first channel material region above the substrate, at least a portion of the first channel material region being between the epitaxial source region and the epitaxial drain region, the first channel material region being coupled to the epitaxial source region and the epitaxial drain region, the first channel material region having a length measured along a first direction that extends from the epitaxial source region to the epitaxial drain region, the length of the first channel material region being great enough to span at least most of a distance between the epitaxial source region and the epitaxial drain region, the first channel material region having a height measured along a second direction that extends up from the substrate, the first channel material region having a width measured along a third direction substantially orthogonal to the first direction and the second direction, the first channel material region comprising a third material, the third material having a third lattice constant, the first channel material region having a first channel region;
a second channel material region above the substrate, at least a portion of the second channel material region being directly above the first channel material region and not in direct contact with the first channel material region, at least a portion of the second channel material region being between the epitaxial source region and the epitaxial drain region, the second channel material region being coupled to the epitaxial source region and the epitaxial drain region, the second channel material region having a length measured along the first direction, the length of the second channel material region being great enough to span at least most of a distance between the epitaxial source region and the epitaxial drain region, the second channel material region having a height measured along the second direction, the second channel material region having a width measured along the third direction, the second channel material region comprising the third material, the second channel material region having a second channel region;
a first gate dielectric layer around the first channel region of the first channel material region, the first gate dielectric layer surrounding the first channel region in a first cross section taken normal to a line extending from the source region to the drain region, the first gate dielectric layer not completely surrounding the first channel region in a second cross section taken through the first channel material region and parallel with a top surface of the substrate, the first gate dielectric layer comprising a first gate dielectric material;
a second gate dielectric layer around the second channel region of the second channel material region, the second gate dielectric layer surrounding the second channel region in a first cross section taken normal to a line extending from the source region to the drain region, the second gate dielectric layer not completely surrounding the second channel region in a second cross section taken through the second channel material region and parallel with a top surface of the substrate, the second gate dielectric layer comprising the first gate dielectric material; and
a gate electrode material around the first channel region of the first channel material region and around the second channel region of the second channel material region, the gate electrode material being separated from the first channel region of the first channel material region by the first gate dielectric layer, the gate electrode material being separated from the second channel region of the second channel material region by the second gate dielectric layer.

12. The device of claim 11 , wherein the second lattice constant is larger than the first lattice constant.

13. The device of claim 11 , wherein the third lattice constant is different than the first lattice constant.

14. The device of claim 11 , wherein the third lattice constant is substantially the same as the second lattice constant.

15. The device of claim 11 , wherein the thi

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Pillarisetty Ravi
• Lee Van H
• Kavalieros Jack T
• Chau Robert S
• Kachian Jessica S

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D30/791 Primary

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title