Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
US-9252229-B2 · Feb 2, 2016 · US
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Ando Takashi patents
Ando Takashi holds 3 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 3 |
| Recent patents | 0 |
| First publication | Jan 27, 2015 |
| Latest publication | Feb 2, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Structure and method to obtain EOT scaled dielectric stacks
US-9059314-B2 · Jun 16, 2015 · US
Low threshold voltage CMOS device
US-8941184-B2 · Jan 27, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
US-9252229-B2 · Feb 2, 2016 · US
Structure and method to obtain EOT scaled dielectric stacks
US-9059314-B2 · Jun 16, 2015 · US
Low threshold voltage CMOS device
US-8941184-B2 · Jan 27, 2015 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10D64/691 | 3 |
| H10D64/667 | 3 |
| H10D64/669 | 3 |
| H10D64/01318 | 2 |
| H10D84/0181 | 2 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 3 |