CMOS-compatible gold-free contacts

Patent metadata

Field	Value
Publication number	US-9252118-B2
Application number	US-201113995689-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor device layer;
a first region of an n-type material, the first region disposed in or on the semiconductor device layer;
a second region of a p-type material, the second region disposed in or on the semiconductor device layer;
a first contact manufactured on the semiconductor device layer with a complementary metal-oxide-semiconductor (CMOS) process, wherein the first contact is disposed directly on a surface of the first region, the first contact including a first layer of a contact material including germanium (Ge) and palladium (Pd), the first layer having a ratio of Ge to Pd that provides for both p-type materials and n-type materials a contact resistivity equal to or less than 6×10 −5 Ohm-cm, wherein the ratio of Ge to Pd is within a range of approximately 1.25-2.0 parts Ge per part Pd;
a second contact manufactured on the semiconductor device layer with the CMOS process, wherein the second contact is disposed directly on a surface of the second region, the second contact including a second layer of the contact material including Ge and Pd, the second layer having the ratio of Ge to Pd.

2. The semiconductor device of claim 1 , wherein the semiconductor device layer comprises an oxide material.

3. The semiconductor device of claim 1 , wherein the first layer of the contact material is in direct contact with a surface of the first region of the n-type material.

4. The semiconductor device of claim 1 , wherein the second layer of the contact material is in direct contact with a surface of the second region of the p-type material.

5. The semiconductor device of claim 1 , wherein the layer of material comprises a layered structure of multiple alternating layers of Ge and Pd that is annealed.

6. The semiconductor device of claim 1 , wherein the layer of contact material comprises a structure formed by depositing a target material that has the ratio of Ge to Pd.

7. The semiconductor device of claim 6 , wherein the layer of material comprises a structure formed by simultaneously depositing the layer of material from at least one Ge target and at least one Pd target.

8. The semiconductor device of claim 1 , the first contact further comprising:
a metal layer adjacent the semiconductor device layer, between the semiconductor device layer and the first layer of contact material.

9. The semiconductor device of claim 8 , wherein the metal layer comprises a layer of titanium.

10. The semiconductor device of claim 8 , wherein the metal layer comprises a layer of tungsten.

11. A semiconductor laser device comprising:
a waveguide region of III-V semiconductor material manufactured onto a silicon substrate with a complementary metal-oxide-semiconductor (CMOS) process, the semiconductor laser device having a layer of oxide manufactured over the III-V semiconductor material, wherein the III-V semiconductor material has a first region of a p-type material exposed through the oxide and a second region of an n-type material exposed through the oxide;
a first contact manufactured directly on the exposed first region, the first contact including a first layer of a contact material including germanium (Ge) and palladium (Pd), the first layer having a ratio of Ge to Pd that provides for both the p-type material and n-type material a contact resistivity equal to or less than 6×10 −5 Ohm-cm, wherein the ratio of Ge to Pd is within a range of approximately 1.25-2.0 parts Ge per part Pd; and
a second contact manufactured directly on the exposed second region, the second contact including a second layer of the contact material including germanium (Ge) and palladium (Pd), the second layer having the ratio of Ge to Pd that provides a low contact resistance for both the p-type material and n-type material.

12. The semiconductor laser device of claim 11 , the contact further comprising:
a layer of metal as a bottom layer adjacent the exposed region; and
an annealed contact stack including multiple alternating layers of germanium (Ge) and palladium (Pd) annealed into a contact material;
wherein the layers of Ge and Pd are disposed on the layer of metal and annealed.

13. The semiconductor laser device of claim 12 , wherein the contact stack is an annealed stack of alternating layers of Ge and Pd with a layer of Ge directly adjacent the layer of metal and a layer of Pd as a top layer of the stack.

14. The semiconductor laser device of claim 13 , wherein the alternating layers of Ge and Pd include:
a bottom layer of Ge having a thickness of approximately 1 unit;
a layer of Pd having a thickness of approximately 1 unit;
a layer of Ge having a thickness of approximately 4 units; and
a top layer of Pd having a thickness of approximately 2 units.

15. The semiconductor laser device of claim 14 , wherein 1 unit is approximately 10 nm.

Assignees

• Jain Siddharth
• Bowers John
• Sysak Matthew
• Heck John
• Feldesh Ran
• Jones Richard
• Shetrit Yoel
• Geva Michael
• Intel Corp
• Univ California

Inventors

• Jain Siddharth
• Bowers John
• Sysak Matthew
• Heck John
• Feldesh Ran
• Jones Richard
• Shetrit Yoel
• Geva Michael

Classifications

• H01S5/04252

  characterised by the material · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10W72/50 Primary

  Bond wires · CPC title

• H01S5/021

  Silicon based substrates · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title