Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9252095-B2
Application number	US-201313922722-A
Country	US
Kind code	B2
Filing date	Jun 20, 2013
Priority date	Jul 9, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate including at least one non-metallized hole;
at least one lower conductive pattern on a bottom surface of the package substrate;
at least one semiconductor chip mounted on the package substrate in a flip-chip bonding manner; and
a mold layer on the package substrate, the mold layer including,
an upper mold portion covering the at least one semiconductor chip and a top surface of the package substrate,

a lower mold portion including a first mold side surface and connected to the upper mold portion through the at least one non-metallized hole to cover at least a portion of the bottom surface of the package substrate and expose at least a portion of the lower conductive pattern, and the lower mold portion including a mold bottom surface defining a lower mold hole exposing the at least one portion of the lower conductive pattern; and
at least one lower solder ball on the lower conductive pattern, the at least one lower solder ball being in direct contact with the first mold side surface.

2. The semiconductor package of claim 1 , wherein
the mold bottom surface is a lowermost surface of the lower mold portion, and
the mold bottom surface has a surface roughness different from that of the first mold side surface.

3. The semiconductor package of claim 2 , wherein the mold bottom surface has a first surface roughness, and the first mold side surface has a second surface roughness greater than the first surface roughness.

4. The semiconductor package of claim 2 , wherein the first mold side surface corresponds to an inner side surface of the lower mold hole.

5. The semiconductor package of claim 1 , further comprising an insulating layer between the bottom surface of the package substrate and the lower mold portion to cover at least a portion of the lower conductive pattern, wherein
the insulating layer includes a lower insulator hole overlapping the lower mold hole, and
an inner width of the lower insulator hole is equivalent to or greater than that of the lower mold hole.

6. The semiconductor package of claim 1 , wherein a height from the bottom surface of the package substrate to the mold bottom surface is less than a height from the bottom surface of the package substrate to a bottom of the lower solder ball.

7. The semiconductor package of claim 1 , wherein the lower mold portion is between adjacent ones of the lower solder balls.

8. The semiconductor package of claim 3 , further comprising an upper solder ball provided on the top surface of the package substrate,
wherein the upper mold portion includes an upper mold hole exposing the upper solder ball, and an inner side surface of the upper mold hole has a surface roughness substantially the same as the second surface roughness.

9. The semiconductor package of claim 8 , further comprising an upper semiconductor package provided on the upper mold portion and electrically connected to the package substrate via the upper solder ball.

10. The semiconductor package of claim 1 , wherein the lower mold portion one of extends from a first edge of the bottom surface of the package substrate to a second edge of the bottom surface opposite the first edge, and substantially covers the bottom surface of the package substrate.

11. The semiconductor package of claim 2 , wherein the lower mold portion has a second mold side surface aligned to a side surface of the package substrate, the second mold side surface having a surface roughness different from the first mold side surface.

12. The semiconductor package of claim 1 , wherein the upper mold portion fills a space between the semiconductor chip and the package substrate.

13. A method of fabricating a semiconductor package, the method comprising:
mounting at least one semiconductor chip on a package substrate in a flip-chip bonding manner, the package substrate including a top surface and a bottom surface facing away from each other, at least one non-metallized hole from the top surface to the bottom surface, and at least one lower conductive pattern provided on the bottom surface;
forming a mold layer including an upper mold portion and a lower mold portion, the upper mold portion covering at least a portion of the top surface of the package substrate, the lower mold portion connected to the upper mold portion through the at least one non-metallized hole and covering at least a portion of the bottom surface of the package substrate; and
removing a portion of the lower mold portion to expose at least a portion of the lower conductive pattern.

14. The method of claim 13 , wherein the removing a portion of the lower mold portion is performed using a laser.

15. The method of claim 13 , further comprising:
attaching a lower solder ball to the lower conductive pattern; and
sequentially cutting the upper mold portion, the package substrate, and the lower mold portion to form unit semiconductor packages separated from each other.

16. The method of claim 13 , wherein the package substrate includes a first upper solder ball attached to the package substrate, the first upper solder ball being covered with the upper mold portion,
the method further comprising removing a portion of the upper mold portion to form an upper mold hole exposing at least a portion of the first upper solder ball.

17. The method of claim 16 , wherein the removing the portion of the lower mold portion and the removing the portion of the upper mold portion use the same process.

18. The method of claim 16 , further comprising:
positioning an upper semiconductor package, the upper semiconductor package including an upper package substrate, an upper semiconductor chip mounted on the upper package substrate, and a second upper solder ball attached to a bottom surface of the upper package substrate, on the upper mold portion so that the first upper solder ball is in contact with the second upper solder ball; and
welding the first and second upper solder balls by providing heat thereto.

19. The method of claim 13 , wherein,
the package substrate includes an insulating layer covering the bottom surface of the package substrate and exposing a portion of the lower conductive pattern, and

the removing the portion of the lower mold portion partially removes the insulating layer.

20. A semiconductor package, comprising:
a package substrate;
a lower conductive pattern on a lower surface of the package substrate;

at least one semiconductor chip mounted above an upper surface of the package substrate in a flip-chip bonding manner; and
a mold layer, the mold layer including,
an upper mold portion over the at least one semiconductor chip and over at least a portion of the upper surface of the package substrate,
a lower mold portion including a mold side surface and covering at least a portion of the lower surface of the package substrate and exposing at least a portion of the lower conductive pattern covered by the lower mold portion,
a connecting portion extending through the package substrate via at least one non-metallized hole and integrally connecting the upper mold portion and the lower mold portion; and

at least one lower solder ball on the lower conductive pattern, the at least one lower solder ball being in direct contact with the mold side surface.

21. The semiconductor package of claim 20 , further comprising:
an insulating layer between the lower surface of the package substrate and the lower mold portion, the insulating layer

Assignees

• Kim Jongkook
• Park su-min
• Park Soojeoung
• Baek Bona
• Im Hohyeuk
• Jang Byoungwook
• Jung Yoonha
• Samsung Electronics Co Ltd

Inventors

• Kim Jongkook
• Park su-min
• Park Soojeoung
• Baek Bona
• Im Hohyeuk
• Jang Byoungwook
• Jung Yoonha

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title