Battery charging circuit with serial connection of MOSFET and an enhancement mode JFET configured as reverse blocking diode with low forward voltage drop

Patent metadata

Field	Value
Publication number	US-9246347-B2
Application number	US-201314101529-A
Country	US
Kind code	B2
Filing date	Dec 10, 2013
Priority date	Sep 29, 2010
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.

First claim

We claim:

1. A battery charging circuit comprising:
a battery having a first battery terminal and a second battery terminal;
a battery charging source having a first charging terminal and a second charging terminal with the first charging terminal connected to the first battery terminal;
a serial connection of a MOSFET and an enhancement mode JFET for bridging the second charging terminal to the second battery terminal, wherein the enhancement mode JFET is configured with its JFET source shorted to its JFET gate thus functions as a reverse blocking diode having a low forward voltage drop.

2. The battery charging circuit of claim 1 wherein,
The MOSFET and the enhancement mode JFET are integrated on a semiconductor die.

3. The battery charging circuit of claim 2 wherein
the semiconductor die comprising:
a lower common semiconductor substrate region (CSSR) of type-1 conductivity;
a MOSFET device region, located at the top of the CSSR, having:
the CSSR as its MOSFET drain region;
at least a MOSFET body region of type-2 conductivity, a MOSFET gate region and a MOSFET source region of type-1 conductivity located at the top of the MOSFET drain region.

4. The battery charging circuit of claim 3 wherein
the semiconductor die further comprising:
a diode-connected enhancement mode JFET (DCE-JFET) device region, located at the top of the CSSR, having:
the CSSR as its DCE-JFET drain region;
at least two DCE-JFET gate regions of type-2 conductivity located at the top of the DCE-JFET drain region and laterally separated from each other along the major CSSR plane with a DCE-JFET gate spacing;
at least a DCE-JFET source region of type-1 conductivity located at the top of the CSSR and between the DCE-JFET gate regions, wherein the DCE-JFET source region is shorted to the DCE-JFET gate regions; and
whereby the CSSR serially connects the MOSFET device drain region to the DCE-JFET device drain region.

5. The battery charging circuit of claim 4 wherein said semiconductor device die further comprises:
two conduction nodes Terminal-S and Terminal-D;
a source electrode connected to the MOSFET source region as the Terminal-S; and
a DCE-JFET electrode in contact with said DCE-JFET gate regions and DCE-JFET source regions, as the Terminal-D.

6. The battery charging circuit of claim 4 wherein said MOSFET-JFET semiconductor device die is connected to a battery and to a battery charging source in a battery charging circuit.

7. The battery charging circuit of claim 4 wherein conductivity level of the DCE-JFET gate regions, conductivity level of a DCE-JFET channel region between the DCE-JFET gate regions and under the DCE-JFET source region, and DCE-JFET gate spacing are all configured at their respectively pre-determined levels whereby making the DCE-JFET device exhibit a low forward voltage Vf and a low reverse leakage current as a diode-connected enhancement mode JFET.

8. The battery charging circuit of claim 7 wherein said Vf is substantially lower than that of a PN junction diode while said reverse leakage current is comparable to that of a PN junction diode.

9. The battery charging circuit of claim 4 wherein:
the dopant material, concentration and depth of the MOSFET body regions are selected to be the same as those of the DCE-JFET gate regions; and
the dopant material, concentration and depth of the MOSFET source regions are selected to be the same as those of the DCE-JFET source regions
whereby simplifying its manufacturing process.

10. The battery charging circuit of claim 5 wherein material and thickness of the MOSFET source electrode is selected to be the same as those of the DCE-JFET electrode whereby simplifying its manufacturing process.

11. The battery charging circuit of claim 4 wherein said MOSFET gate regions are configured as trench gates extending downwards into the MOSFET body regions and the CSSR.

12. The battery charging circuit of claim 4 wherein said MOSFET gate regions are configured as planar gates located over the MOSFET body regions and bridging the MOSFET source regions to the CSSR.

13. The battery charging circuit of claim 4 where said CSSR comprises an upper layer of lower type-1 conductivity atop a lower substrate layer of higher type-1 conductivity.

14. The battery charging circuit of claim 4 wherein said type-1 conductivity is P-type and said type-2 conductivity is N-type whereby making the MOSFET-JFET semiconductor device die a P-channel device.

15. The battery charging circuit of claim 4 wherein said type-1 conductivity is N-type and said type-2 conductivity is P-type whereby making the MOSFET-JFET semiconductor device die an N-channel device.

16. The battery charging circuit of claim 1 wherein the semiconductor device die is a discrete power device.

Assignees

• Lui Sik
• Wang Wei
• Alpha & Omega Semiconductor

Inventors

• Lui Sik
• Wang Wei

Classifications

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H02J7/0052

  Electricity · mapped topic

• H02J7/0072 Primary

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic