Semiconductor structure having buried conductive elements

Patent metadata

Field	Value
Publication number	US-9245892-B2
Application number	US-201414184756-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Feb 20, 2014
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first conductor horizontally formed on a semiconductor substrate;
a second conductor vertically formed in a semiconductor stack that includes the semiconductor substrate;
an oxidized region formed proximate to the first conductor;
wherein the second conductor is formed in a manner to be in electrical communication with the first conductor;
wherein the first conductor is formed in a manner to be laterally connected to the second conductor; and
wherein the first conductor is formed in a manner to not traverse beneath the oxidized region; and
wherein the first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

2. The semiconductor structure of claim 1 , wherein the first conductor includes epitaxially grown conducting material.

3. The semiconductor structure of claim 2 , wherein the epitaxially grown conducting material includes an n-type or p-type dopant.

4. The semiconductor structure of claim 1 , wherein the first conductor is in electrical communication with a common backside plate.

5. The semiconductor structure of claim 1 , wherein the second conductor is a trench metal-insulator-metal capacitor.

6. The semiconductor structure of claim 1 , further comprising a fin located in the semiconductor stack.

7. The semiconductor structure of claim 6 , wherein the second conductor is located proximate to the fin.

8. The semiconductor structure of claim 1 , wherein the second conductor is formed distal or proximate to the oxidized region.

9. The semiconductor structure of claim 1 , wherein the second conductor is a through-silicon-via.

10. The semiconductor structure of claim 1 , wherein the first conductor is a self-aligned landing pad.

Assignees

• IBM

Inventors

• Alptekin Emre
• Batra Pooja R
• Cheng Kangguo
• Divakaruni Ramachandra
• Faltermeier Johnathan E
• Vega Reinaldo A

Classifications

• H10W20/046

  the barrier, adhesion or liner layers being associated with interconnections of capacitors · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/021 Primary

  of interconnections within wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title