Deep collector vertical bipolar transistor with enhanced gain

Patent metadata

Field	Value
Publication number	US-9245755-B2
Application number	US-201414575552-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 30, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

First claim

What is claimed is:

1. A process of forming an integrated circuit, comprising the steps:
providing a substrate wafer with a first doping type;
implanting a first implant of a second doping type to form a deep well in the substrate wafer wherein the deep well forms a collector of a deep collector vertical bipolar transistor;
implanting a second implant of the second doping type to form a first well in the substrate wafer wherein the first well contacts the deep well and electrically isolates a base region of the deep collector vertical bipolar transistor from the substrate;
implanting the second implant to form a second well in the substrate wherein the second well forms a body of a MOS transistor;
forming a MOS transistor gate dielectric;
forming a MOS transistor gate on the MOS transistor gate dielectric;
implanting a third implant of the second doping type to form source and drain diffusions self aligned to the MOS transistor gate;
implanting the third implant to form an emitter of the deep collector vertical bipolar transistor;
implanting a fourth implant of the first doping type to form a first base tuning diffusion within the base of the deep collector vertical bipolar transistor; and
implanting the fourth implant to form a second base tuning diffusion under the gate of the MOS transistor gate and under the source and drain diffusions.

2. The process of claim 1 , wherein the first doping type is p-type, the second doping type is n-type, the MOS transistor is an NMOS transistor and the deep collector vertical bipolar transistor is a deep collector vertical NPN bipolar transistor.

3. The process of claim 1 , wherein the fourth implant is boron with a dose in the range of 1E12/cm 2 and 1E13/cm 2 .

4. The process of claim 1 , wherein the fourth implant is boron with a dose between 1E12/cm 3 and 1E13/cm 3 with an energy between 60 keV and 140 keV.

5. The process of claim 1 , wherein the first doping type is n-type, the second doping type is p-type, the MOS transistor is a PMOS transistor and the deep collector vertical bipolar transistor is a deep collector vertical PNP bipolar transistor.

6. The process of claim 5 , wherein the fourth implant is phosphorus with a dose in the range of 1E12/cm 2 and 1E13/cm 2 .

7. The process of claim 5 , wherein the fourth implant is phosphorus with a dose between 1E12/cm 3 and 1E13/cm 3 with an energy between 60 keV and 140 keV.

8. A process of forming an integrated circuit, comprising the steps:
providing a p-type substrate wafer;
implanting phosphorus to form a deep nwell wherein the deep nwell forms a collector of a deep collector vertical NPN bipolar transistor;
implanting phosphorus dopant to form an nwell in the p-type substrate wafer wherein the nwell forms electrical contact to the deep nwell and surrounds a p-type base region of the deep collector vertical NPN bipolar transistor;
forming a transistor gate dielectric;
forming an NMOS transistor gate on the transistor gate dielectric;
implanting at least one of arsenic and phosphorus to form NMOS source and drain diffusions self aligned to the NMOS transistor gate and to form an emitter of the deep collector vertical NPN bipolar transistor; and
implanting boron to form a first base tuning diffusion within the p-type base of the deep collector vertical NPN bipolar transistor and to form a second base tuning diffusion under the NMOS transistor gate and under the NMOS source and drain diffusions.

9. The process of claim 8 , wherein a concentration of boron in the first and second tuning diffusion implants is in the range of 1E12/cm 3 and 1E13/cm 3 .

10. The process of claim 8 , wherein a concentration of boron in the first and second tuning diffusion implants is between 1E12/cm 3 and 1E13/cm 3 implanted with an energy between 60 keV and 140 keV.

11. A process of forming an integrated circuit, comprising the steps:
providing an n-type substrate wafer;
implanting boron to form a deep pwell wherein the deep pwell forms a collector of a deep collector vertical PNP bipolar transistor;
implanting boron dopant to form a pwell in the n-type substrate wafer wherein the pwell forms electrical contact to the deep pwell and surrounds an n-type base region of the deep collector vertical PNP bipolar transistor;
forming a transistor gate dielectric;
forming a PMOS transistor gate on the transistor gate dielectric;
implanting at least one of boron and BF 2 to form PMOS source and drain diffusions self-aligned to the PMOS transistor gate and to form an emitter of the deep collector vertical PNP bipolar transistor; and
implanting phosphorus to form a first base tuning diffusion within the n-type base of the deep collector vertical PNP bipolar transistor and to form a second base tuning diffusion under the PMOS transistor gate and under the PMOS source and drain diffusions.

12. The process of claim 8 , wherein a concentration of phosphorus in the first and second tuning diffusion implants is in the range of 1E12/cm 3 and 1E13/cm 3 .

13. The process of claim 8 , wherein a concentration of phosphorus in the first and second tuning diffusion implants is between 1E12/cm 3 and 1E13/cm 3 implanted with an energy between 60 keV and 140 keV.

Assignees

• Texas Instruments Inc

Inventors

• Hornung Brian E
• Bo Xiang-Zheng
• Chatterjee Amitava
• Tsao Alwin J

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title