Memory stacks management

Patent metadata

Field	Value
Publication number	US-9244860-B2
Application number	US-201514633708-A
Country	US
Kind code	B2
Filing date	Feb 27, 2015
Priority date	Dec 9, 2010
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

First claim

What is claimed is:

1. A method for managing a memory stack, the method comprising:
mapping a first part of the memory stack to a span of fast memory and a second different part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory; and
changing a value of a control bit of a virtual page on the fast memory to an unavailable status upon mapping the first part of the memory stack to the virtual page.

2. The method of claim 1 , wherein the fast memory is tightly integrated with a processor.

3. The method of claim 1 , wherein the slow memory is not tightly integrated with a processor.

4. The method of claim 1 , wherein if the memory stack is an upward growing stack, mapping a bottom part of the memory stack to the fast memory.

5. The method of claim 4 , wherein mapping the memory stack further comprises:
providing a first virtual address space and a second virtual address space;
dividing each of the span of the fast memory, the span of the slow memory, the first virtual address space, and the second virtual address space into a pre-determined number of equal sized pages;
mapping a first page of the first virtual address space to a first page of the fast memory; and
mapping the bottom part of the memory stack to the first page of the first virtual address space.

6. The method of claim 5 , further comprising, mapping a corresponding first page of the second virtual address space to a page of the slow memory.

7. The method of claim 6 , further comprising:
if a size of the memory stack is larger than a size of a page of the fast memory:
mapping a second page of the first virtual address space above the first page to the slow memory, and
mapping an incremental part of the memory stack to the second page of the first virtual address space.

8. The method of claim 6 , further comprising:
providing a memory management unit, the memory management unit having a plurality of bits, each of the plurality of bits identifying mapping of a page of the first virtual address space.

9. The method of claim 1 , wherein if the memory stack is a downward growing stack, a part of the stack mapped to the fast memory is a top part of the memory stack.

10. A method of optimizing tightly integrated memory (TIM) usage, the method comprising:
mapping a first part of a memory stack to a span of TIM address space;
mapping a second part of the memory stack to a span of non-TIM memory address space; and
changing a value of a control bit of a virtual page on the TIM address space to an unavailable status upon mapping the first part of memory stack to the virtual page.

11. The method of claim 10 , wherein the first part of the memory stack is an initial part of the memory stack.

12. The method of claim 11 , further comprising:
dividing the span of TIM address space into a first number of pages;
providing a first number of virtual address spaces;
dividing each of the virtual address spaces into a second number of pages, wherein a size of each of the second number of pages is equal to a size of the first number of pages;
mapping a bottom page of one of the first number of virtual address spaces to a TIM page; and
mapping the initial part of a memory stack to the bottom page of the one of the first number of virtual address spaces.

13. The method of claim 12 , further comprising:
mapping a page above the bottom page of the one of the first number of virtual address spaces to a slow memory page; and
mapping a part of the memory stack above the initial part of the memory stack to the page above a bottom page.

14. The method of claim 13 , further comprising:
mapping each page of the virtual address spaces other than a bottom page to a slow memory.

15. The method of claim 12 , further comprising:
providing a control unit comprising a number of control bits equal to the first number of pages, wherein each control bit represents the availability status of a corresponding TIM page.

16. The method of claim 15 , further comprising:
determining when a stack mapped to a TIM page corresponding to the one of the control bits is not in use; and
changing the value of the one of the control bits to an available status.

17. One or more non-transitory computer-readable storage medium encoding computer-executable instructions for executing on a computer system a computer process, the computer process comprising:
mapping a first part of a memory stack to span a fast memory and a second different part of the memory stack to span a slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory; and
changing a value of a control bit of a virtual page on the fast memory to an unavailable status upon mapping the first part of memory stack to the virtual page.

18. The one or more non-transitory computer-readable storage medium of claim 17 , wherein the fast memory is tightly integrated with a processor.

19. The one or more non-transitory computer-readable storage medium of claim 17 , wherein the part of a memory stack mapped to span a fast memory is an initial part of the memory stack, wherein the fast memory is tightly integrated with a processor.

Assignees

• Seagate Technology Llc

Inventors

• Gaertner Mark
• Heath Mark Alan

Classifications

• G06F12/0284 Primary

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F7/785

  having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title