Run-to-run control utilizing virtual metrology in semiconductor manufacturing

Patent metadata

Field	Value
Publication number	US-9240360-B2
Application number	US-201213557955-A
Country	US
Kind code	B2
Filing date	Jul 25, 2012
Priority date	Jul 25, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A method for run-to-run control and sampling optimization in a semiconductor manufacturing process includes the steps of: determining a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; determining a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; and controlling at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error.

First claim

What is claimed is:

1. A method for run-to-run control and sampling optimization in a semiconductor manufacturing process, the method comprising steps of:
determining a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process;
determining a predicted process output and corresponding prediction error associated with a virtual metrology for the current semiconductor manufacturing processing run;
assigning a first weight to the metrology error and a second weight to the prediction error, the first and second weights being indicative of a confidence in the metrology error and prediction error, respectively; and
controlling at least one parameter corresponding to a subsequent semiconductor manufacturing processing run as a function of the metrology error, the first and second weights, and the prediction error;
wherein said semiconductor manufacturing process is executed to fabricate at least one wafer.

2. The method of claim 1 , wherein the steps of determining the process output and corresponding metrology error comprises:
measuring at least one target processing parameter corresponding to a wafer fabricated in the current processing run;
comparing the measured at least one target processing parameter with an expected value for the at least one target processing parameter; and
determining the metrology error as a function of a variation between the measured at least one target processing parameter and the expected value for the at least one target processing parameter.

3. The method of claim 1 , wherein the steps of determining the predicted process output and corresponding prediction error comprises:
obtaining a prediction model associated with the semiconductor manufacturing process, the prediction model adapted to predict the process output by estimating at least one processing parameter for the semiconductor manufacturing process; and
performing virtual metrology based on the prediction model, the prediction error being determined as a function of an output of the virtual metrology.

4. The method of claim 3 , wherein the prediction model comprises at least one of a single processing chamber based model, a global model across a plurality of processing chambers, a metrology-based prediction model, and a metrology and error-adaptive model.

5. The method of claim 4 , wherein the global model is generated by approximating coefficients corresponding to different processing chambers to a common vector given by prior information on tool capability matching, adding a positive coefficient to balance different terms in the global model, and minimizing the prediction error and optimizing the approximation.

6. The method of claim 5 , wherein optimizing the approximation comprises using a block coordinate based algorithm.

7. The method of claim 4 , further comprising constructing the metrology-based prediction model by:
obtaining a plurality of predictors, the predictors comprising information relating to the semiconductor manufacturing process;
decomposing the predictors into at least two types, a first type comprising variance profiles, and a second type obtained based on dynamic regression models; and
generating a combined predictor comprising at least a subset of the first type of predictors and at least a subset of the second type of predictors.

8. The method of claim 1 , wherein the first and second weights are dynamically adjusted in accordance with a confidence in the metrology error and prediction error, respectively, over time.

9. The method of claim 1 , wherein each of the first and second weights is a percentage, with a sum of the first and second weights being equal to one.

10. The method of claim 1 , further comprising optimizing a sampling policy corresponding to the semiconductor manufacturing process as a function of the first and second weights.

11. The method of claim 10 , wherein the step of optimizing the sampling policy comprises maximizing a time between actual metrology measurements obtained in connection with the semiconductor manufacturing process.

12. The method of claim 1 , wherein respective values of the first and second weights are determined as a function of one or more factors related to uncertainty and chamber matching capabilities associated with the semiconductor manufacturing process.

13. A method for run-to-run control and sampling optimization in a semiconductor manufacturing process, the method comprising steps of:
determining a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process;
determining a predicted process output and corresponding prediction error associated with a virtual metrology for the current semiconductor manufacturing processing run; and
controlling at least one parameter corresponding to a subsequent semiconductor manufacturing processing run as a function of the metrology error and the prediction error;
wherein the steps of determining the predicted process output and corresponding prediction error comprises:
obtaining a prediction model associated with the semiconductor manufacturing process, the prediction model adapted to predict the process output by estimating at least one processing parameter for the semiconductor manufacturing process; and
performing virtual metrology based on the prediction model, the prediction error being determined as a function of an output of the virtual metrology;

wherein the prediction model comprises a wafer quality prediction model for metrology variable prediction which utilizes tensor input process variables by directly operating on the tensor input process variables.

14. A method for run-to-run control and sampling optimization in a semiconductor manufacturing process, the method comprising steps of:
determining a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process;
determining a predicted process output and corresponding prediction error associated with a virtual metrology for the current semiconductor manufacturing processing run;
controlling at least one parameter corresponding to a subsequent semiconductor manufacturing processing run as a function of the metrology error and the prediction error;
assigning a first weight to the metrology error and a second weight to the prediction error, the first and second weights being indicative of a confidence in the metrology error and prediction error, respectively;
controlling the at least one parameter corresponding to a subsequent processing run as a function of the first and second weights; and
optimizing a sampling policy corresponding to the semiconductor manufacturing process as a function of the first and second weights;
wherein the step of optimizing the sampling policy comprises at least one of: minimizing a sampling frequency of the semiconductor manufacturing process, the sampling frequency being indicative of at least one of a number of processing runs and a number of wafers between consecutive metrology measurements obtained during actual metrology; and maximizing a time between actual metrology measurements obtained in connection with the semiconductor manufacturing process.

15. A method for run-to-run control and sampling optimization in a semiconductor manufacturing process, the method comprising steps of:
determining a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semicon

Assignees

• Baseman Robert Jeffrey
• He Jingrui
• Yashchin Emmanuel
• Zhu Yada
• IBM

Inventors

• Baseman Robert Jeffrey
• He Jingrui
• Yashchin Emmanuel
• Zhu Yada

Classifications

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G05B13/048

  using a predictor · CPC title

• G05B19/41875

  characterised by quality surveillance of production · CPC title

• H01L22/20 Primary

  Electricity · mapped topic

• G05B2219/32182

  If state of tool, product deviates from standard, adjust system, feedback · CPC title