Hierarchical testing architecture using core circuit with pseudo-interfaces

Patent metadata

Field	Value
Publication number	US-9239897-B2
Application number	US-201414243602-A
Country	US
Kind code	B2
Filing date	Apr 2, 2014
Priority date	Apr 3, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.

First claim

What is claimed is:

1. A core circuit in a test circuit comprising:
at least one real input configured to receive scan-in data and control data for controlling operation of the core circuit from a source external to the test circuit;
an input register chain coupled to the at least one real input and configured to store the scan-in data and the control data;
at least one scan chain coupled to a subset of registers in the register chain to receive the scan-in data and configured to generate a scan-out data representing presence of faults in an associated circuit responsive to receiving the scan-in data;
a pseudo-output coupled to the input register chain and configured to send at least a subset of the scan-in data and the control data to another input register chain in the core circuit or to another core circuit; and
a pseudo-input coupled to the input register chain, the pseudo input coupled directly to a pseudo output of the core circuit or the other core circuit.

2. The core circuit of claim 1 , further wherein the pseudo-input is coupled to a portion of the input register chain for storing a subset of the scan-in data.

3. The core circuit of claim 1 , wherein the pseudo-output is coupled to a portion of the input register chain for storing a subset of the scan-in data.

4. The core circuit of claim 3 , wherein:
the pseudo-output of the core circuit is coupled to a real input of the other core circuit, the pseudo-input of the core circuit coupled to a pseudo-input of the other core circuit.

5. The core circuit of claim 3 , wherein the at least one real input of the core circuit is coupled to a real input of another core circuit.

6. The core circuit of claim 5 , wherein:
the pseudo-output of the core circuit is coupled to the data pseudo-input of the core circuit, and
a pseudo-output of the other core circuit is coupled to a pseudo-input of the other core circuit.

7. The core circuit of claim 1 , wherein the pseudo-output of the core circuit is coupled to a portion of the input register chain for string a subset of the control data.

8. The core circuit of claim 7 , wherein the pseudo-output of the core circuit is coupled to a pseudo-input of the other core circuit.

9. The core circuit of claim 7 , wherein a pseudo-output of the other core circuit is coupled to a pseudo-input of the other core circuit.

10. The core circuit of claim 1 , further comprising:
a compressor coupled to the at least one scan chain to compress the scan-out data; and
at least one first scan-out pseudo input coupled to an output of the compressor and configured to receive data from an output register of the core circuit or another core circuit, the at least one first scan-out pseudo-input to be combined with an output of the compressor.

11. The core circuit of claim 10 , wherein the at least first scan-out pseudo-input is combined with the output of the compressor by an XOR operator.

12. The core circuit of claim 10 , further comprising:
an output register coupled to the compressor and configured to store compressed data derived from the scan-out data and an input signal received via the first pseudo input; and
at least a second scan-out pseudo input coupled to the output register and configure to receive data from another output register of the core circuit or another core circuit, the at least one second scan-out pseudo-input to be combined with an output of the output register.

13. The core circuit of claim 12 , wherein the at least one second scan-out pseudo-input is combined with the output of the output register by an XOR operation.

14. The core circuit of claim 10 , wherein:
the output of the output register of the core circuit is coupled to a first scan-out pseudo-input of another core circuit; and
the at least one first scan-out pseudo-input of the core circuit is coupled to ground.

15. The core circuit of claim 10 , further comprising:
the output of the output register of the core circuit is coupled to a second scan-out pseudo-input of another core circuit; and
the at least second scan-out pseudo-input of the core circuit is coupled to ground.

16. A non-transitory computer-readable medium storing a design of a core circuit for including in a test circuit, the design of the core circuit comprising:
at least one real input configured to receive scan-in data and control data for controlling operation of the core circuit from a source external to the test circuit;
an input register chain coupled to the at least one real input and configured to store the scan-in data and the control data;
at least one scan chain coupled to a subset of registers in the register chain to receive the scan-in data and configured to generate a scan-out data representing presence of faults in an associated circuit responsive to receiving the scan-in data;
a pseudo-output coupled to the input register chain and configured to send at least a subset of the scan-in data and the control data to another input register chain in the core circuit or to another core circuit; and
a pseudo-input coupled to the input register chain, the pseudo input coupled directly to a pseudo output of the core circuit or the other core circuit.

17. The non-transitory computer-readable medium of claim 16 , wherein the pseudo-input is coupled to a portion of the input register chain for storing a subset of the scan-in data.

18. The non-transitory computer-readable medium of claim 16 , wherein the pseudo-output is coupled to a portion of the input register chain for storing a subset of the scan-in data.

19. A non-transitory computer-readable medium storing instructions for generating a design of a test circuit, the instructions when executed by a processor cause the processor to:
receive one or more parameters for generating a design of a test circuit, the one or more parameters including a description of one or more test core circuits;
generate a core circuit based on the received one or more parameters, the test core circuit including:
at least one real input configured to receive scan-in data and control data for controlling operation of the core circuit from a source external to the test circuit;
an input register chain coupled to the at least one real input and configured to store the scan-in data and the control data;
at least one scan chain coupled to a subset of registers in the register chain to receive the scan-in data and configured to generate a scan-out data representing presence of faults in an associated circuit responsive to receiving the scan-in data;
a pseudo-output coupled to the input register chain and configured to send at least a subset of the scan-in data and the control data to another input register chain in the core circuit or to another core circuit; and
a pseudo-input coupled to the input register chain, the pseudo input coupled directly to a pseudo output of the core circuit or the other core circuit; and

generate connections for at least one of the pseudo-outputs and at least one of the pseudo-inputs based on the received one or more parameters.

Assignees

• Synopsys Inc

Inventors

• Chebiyam Subramanian B
• Kulkarni Santosh
• Chandra Anshuman
• Kapur Rohit

Classifications

• G01R31/318547 Primary

  Data generators or compressors · CPC title

• G06F30/30 Primary

  Circuit design · CPC title

• G06F17/5045 Primary

  Physics · mapped topic