Test access architecture for TSV-based 3D stacked ICS

Patent metadata

Field	Value
Publication number	US-9239359-B2
Application number	US-201213626538-A
Country	US
Kind code	B2
Filing date	Sep 25, 2012
Priority date	Mar 26, 2010
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

First claim

What is claimed is:

1. A die comprising test circuitry configured to test the die and further configured to test interconnections between the die and another die, the test circuitry comprising:
a first input port configured to receive test stimuli;
a first output port configured to send test responses, the first input port and the first output port being located at a first major surface on a same side of the die,
wherein the test circuitry includes a data signal path within the die between the first input port and the first output port, such that the circuitry is configured to test the die using the test stimuli received through the first input port;
at least one second output port configured to send test stimuli towards the other die; and
at least one second input port configured to receive test responses from the other die,
wherein the test circuitry includes a data signal path within the die between the first input port and at least one of the second output ports, and wherein the test circuitry includes a data signal path within the die between at least one of the second input ports and the first output port, such that the test circuitry is configured to test the other die using the test stimuli sent towards the other die.

2. The die according to claim 1 , further comprising a number of switches configured to switch between a mode for sending signals over the data signal path within the die between the first input port and the first output port and a mode for sending signals within the die between at least one of the second input ports and the first output port.

3. The die according to claim 1 , further comprising an instruction register configured to load and store instructions determining whether test responses will be sent towards one of the first output port from either one of the first input port or from one of the at least one second input ports.

4. The die according to claim 1 , further comprising at least one registration element in the signal path between the first input port and the at least one second output port and at least one registration element in the signal path between the at least one second input port and the first output port.

5. The die according to claim 1 , further comprising at least one further input port and/or at least one further output port for facilitating pre-bond die testing, the at least one further input port and/or at least one further output port being connected to the data signal path between the first input port and the first output port and/or to the data signal path between the first input port and at least one of the second output ports, and/or to the data signal path between at least one of the second input ports and the first output port.

6. The die according to claim 5 , further comprising detection circuitry configured to automatically detect whether the die is in pre-bond or post-bond configuration.

7. The die according to claim 6 , wherein the detection circuitry is configured to generate a control signal for selecting between the at least one first input port and the at least one further input port.

8. The die according to claim 1 , comprising at least two second output ports configured to send test stimuli towards the other die and at least two second input port configured to receive test responses from the other die, wherein there is a data signal path within the die between the first input port and at least one of the second output ports, and wherein there is a data signal path within the die between at least one of the second input ports and the first output port.

9. A stack comprising at least one die according to claim 1 .

10. The stack according to claim 9 , wherein the stack comprising at least a first and a second die, wherein a second output port of the first die is connected to a first input port of the second die, and a first output port of the second die is connected to a second input port of the first die.

11. The stack according to claim 9 , wherein at least one die comprises external input/output ports.

12. The stack according to claim 9 , wherein a plurality of instruction registers associated with different dies are concatenated in a register chain.

13. The stack according to claim 12 , wherein at least one die in the stack comprises at least one embedded core provided with at least one core-level instruction register, wherein the register chain is a hierarchical instruction register chain adapted for operation such that a die-level instruction register instruction determines whether core-level instruction registers are bypassed.

14. The stack according to claim 12 , wherein at least one die in the stack has at least one other die stacked thereon, wherein the register chain is a hierarchical instruction register chain adapted for operation such that a die-level instruction register instruction determines whether the die-level instruction register of the at least one other die is bypassed.

15. A method of testing a stack of dies comprising a bottom die and a top die stacked on top of the bottom die, the method comprising:
applying a test signal to the bottom die;
determining whether the bottom die is to be tested, whether the top die is to be tested, or whether interconnections between the bottom die and the top die are to be tested;
depending on the determination, routing the test signal over a data signal path within the bottom die or through interconnections between the bottom die and the top die; and
receiving a test response from the stack at the bottom die.

16. A non-transitory computer readable medium having stored thereon instructions which, when executed on a processor, carries out a method of claim 15 .

17. The method of claim 15 , wherein the method is performed by a processor.

18. A method of designing a testable die, the method comprising:
receiving a software representation of the die; and
modifying the software representation of the die, the die representation modifying comprising:
adding a first input port for receiving test stimuli and a first output port for sending test responses, the first input port and the first output port being located at a same side of the die,
providing a data signal path within the die between the first input port and the first output port,
adding at least one second output port for sending test stimuli towards another die and at least one second input port for receiving test responses from the another die, and
providing a data signal path within the die between the first input port and at least one of the second output ports, and a data signal path within the die between at least one of the second input ports and the first output port.

19. A non-transitory computer readable medium having stored thereon instructions which, when executed on a processor, carries out a method of claim 18 .

20. The method of claim 18 , wherein the method is performed by a processor.

Assignees

• Imec
• Stichting Imec Nederland

Inventors

• Marinissen Erik Jan
• Verbree Jacobus
• Konijnenburg Mario
• Chi Chun-Chuan

Classifications

• G01R31/31717

  Interconnect testing (by scan techniques see G01R31/31855) · CPC title

• G01R31/318572

  Input/Output interfaces · CPC title

• G01R31/318511

  Wafer Test · CPC title

• G01R31/318513

  Test of Multi-Chip-Moduls · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title