Methods and apparatus for testing inaccessible interface circuits in a semiconductor device
US-9213054-B2 · Dec 15, 2015 · US
US8977919B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977919-B2 |
| Application number | US-201313765260-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 12, 2013 |
| Priority date | Feb 21, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.
Opening claim text (preview).
The invention claimed is: 1. An integrated circuit die comprising: A. a bottom surface including Parallel Test Input (PTI) contact points, a Test Data input (TDI) contact point, Test Control Input (TCI) contact points, a Test Data Output (TDO) contact point, and Parallel Test Input/Output (PTIO) contact points; B. a top surface including PTO contact points, a TDO contact point, Test Control Output (TCO) contact points, a TDI contact point, and PTIO contact points; C. a Test Co…
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