Wiring substrate, semiconductor device, and method for manufacturing thereof

US9237657B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9237657-B2
Application numberUS-201213349821-A
CountryUS
Kind codeB2
Filing dateJan 13, 2012
Priority dateOct 28, 2003
Publication dateJan 12, 2016
Grant dateJan 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention provides a thin wiring pattern such as wiring formed by discharging a droplet. In the present invention, a porous (including microporous) substance is formed as a base film in forming pattern by using a droplet discharge method (also referred to as an ink-jetting method). One feature of a wiring substrate according to the present invention provides a porous film and a conductive layer thereon. One feature of a semiconductor device of the present invention provides a thin film transistor in which a gate electrode is formed by the conductive layer having the above-described structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a wiring substrate, comprising the steps of: forming a first conductive layer; forming an insulating layer over the first conductive layer; forming a porous film on the insulating layer; forming an opening in the insulating layer and the porous film; discharging a composition including a conductive material into the opening and over the porous film to form a second conductive layer to be on and in direct contact with the fi…

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What does patent US9237657B2 cover?
The present invention provides a thin wiring pattern such as wiring formed by discharging a droplet. In the present invention, a porous (including microporous) substance is formed as a base film in forming pattern by using a droplet discharge method (also referred to as an ink-jetting method). One feature of a wiring substrate according to the present invention provides a porous film and a cond…
Who is the assignee on this patent?
Maekawa Shinji, Arai Yasuyuki, Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H05K3/1208. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).