Clock data recovery circuit

Patent metadata

Field	Value
Publication number	US-9237004-B2
Application number	US-201314028219-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Sep 16, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

First claim

What is claimed is:

1. A clock data recovery circuit comprising:
a recovery unit generating a recovery clock signal according to an original data signal, wherein the recovery unit comprises a first frequency divider, the first frequency divider divides a frequency of the recovery clock signal by N to generate a first dividing signal, and N is a positive integer; and
a loop control unit comprising a second frequency divider and a locking detector, wherein the second frequency divider divides the frequency of the recovery clock signal by M to generate a second dividing signal, and the locking detector detects a frequency difference between a reference clock signal and the second dividing signal, M is positive integer and M is greater than N,
when the frequency difference between the reference clock signal and the second dividing signal is not within a preset frequency range, the loop control unit switches the recovery unit to a first loop, and the recovery unit adjusts the frequency of the recovery clock signal according to the reference clock signal and the first dividing signal, so as to lock the frequency of the recovery clock signal to a correction frequency, and
when the frequency difference between the reference clock signal and the second dividing signal is within the preset frequency range, the loop control unit switches the recovery unit to a second loop, and the frequency of the recovery clock signal is locked to a sampling frequency from the correction frequency in response to the second loop, wherein the correction frequency is smaller than the sampling frequency.

2. The clock data recovery circuit as recited in claim 1 , wherein when the frequency of the recovery clock signal is locked to the sampling frequency, the recovery unit samples the original data signal by the recovery clock signal so as to generate a recovery data signal.

3. The clock data recovery circuit as recited in claim 1 , wherein the recovery unit further comprises:
a phase frequency detector detecting a phase difference and a frequency difference between the reference clock signal and the first dividing signal, and generating a first pulse signal according to a detection result;
a charge pump, wherein the charge pump performs charging or discharging in the first loop according to the first pulse signal so as to generate a clock control signal; and
a voltage controlled oscillator generating the recovery clock signal, and adjusting the frequency of the recovery clock signal according to the clock control signal.

4. The clock data recovery circuit as recited in claim 3 , wherein the voltage controlled oscillator further generate a shift clock signal, and the recovery unit further comprises:
a phase detector using the recovery clock signal and an inverted signal of the recovery clock signal to sample the original data signal, so as to generate a second pulse signal; and
a frequency detector connected in parallel with the phase detector, and sampling the original data signal by the recovery clock signal, the shift clock signal and an inverted signal of the shift clock signal, so as to generate a third pulse signal, wherein the charge pump performs charging or discharging in the second loop according to the second pulse signal and the third pulse signal so as to generate the clock control signal.

5. The clock data recovery circuit as recited in claim 4 , wherein the recovery unit further comprises:
a multiplexer electrically connected to an output terminal of the phase frequency detector, an output terminal of the phase detector and an input terminal of the charge pump, and the multiplexer connecting the input terminal of the charge pump to the output terminal of the phase frequency detector or the output terminal of the phase detector according to a loop control signal from the loop control unit.

6. The clock data recovery circuit as recited in claim 5 , wherein when the loop control signal is switched to a first level, the multiplexer connects the input terminal of the charge pump to the output terminal of the phase frequency detector for enabling the recovery unit to form the first loop, and when the loop control signal is switched to a second level, the multiplexer connects the input terminal of the charge pump to the output terminal of the phase detector for enabling the recovery unit to form the second loop.

7. The clock data recovery circuit as recited in claim 6 , wherein when the frequency difference between the reference clock signal and the second dividing signal is not within the preset frequency range, the loop control unit switches the loop control signal to the first level, and when the frequency difference between the reference clock signal and the second dividing signal is within the preset frequency range, the loop control unit switches the loop control signal to the second level.

8. The clock data recovery circuit as recited in claim 1 , wherein
the locking detector determines whether the frequency difference between the reference clock signal and the second dividing signal is within the preset frequency range, and switches the level of a loop control signal according to a determined result.

9. The clock data recovery circuit as recited in claim 8 , wherein when the frequency difference between the reference clock signal and the second dividing signal is not within the preset frequency range, the locking detector switches the loop control signal to a first level for enabling the recovery unit to be switched to the first loop, and when the frequency difference between the reference clock signal and the second dividing signal is within the preset frequency range, the locking detector switches the loop control signal to a second level for enabling the recovery unit to be switched to the second loop.

10. The clock data recovery circuit as recited in claim 1 further comprising:
an equalizer configured to amplify the original data signal.

Assignees

• Himax Tech Ltd

Inventors

• Lin Shih-Chun

Classifications

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H04L7/0004

  Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence) · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/113

  using frequency discriminator · CPC title