Field effect transistor

Patent metadata

Field	Value
Publication number	US-9236494-B2
Application number	US-201213710427-A
Country	US
Kind code	B2
Filing date	Dec 10, 2012
Priority date	Dec 13, 2011
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A field effect transistor (FET) is provided. The active layer of this FET is composed of at least two different amorphous metal oxide semiconductor layer stacked together. Therefore, the two opposite surfaces of the active layer can have different band gap values.

First claim

What is claimed is:

1. A field effect transistor, comprising;
a gate;
a gate insulating layer;
an active layer having a first surface and a second surface opposite to the first surface, wherein the gate, the gate insulating layer and the active layer are sequentially stacked on a substrate, the active layer has a first metal oxide semiconductor layer and a second metal oxide semiconductor layer different from each other, the first metal oxide semiconductor layer is physically in contact with the second metal oxide semiconductor layer, and the first and second metal oxide semiconductor layers constitute a heterojunction of indium gallium zinc oxide and indium gallium zinc calcium oxide; and
a source arid a drain respectively connecting to the active layer.

2. The field effect transistor of claim 1 , wherein the first and second surfaces respectively have a first band gap value and a second band gab value, and a difference between the first band gap value and the second band gap value is at least 0.5 eV.

3. The field effect transistor of claim 2 , wherein the difference between the first band gap value and the second band gap value is at least 1 eV.

4. The field effect transistor of claim 2 , wherein the first band gap value at the first surface is gradually changed to the second band gap value at the second surface of the active layer.

5. The field effect transistor of claim 1 , wherein the gate, the source and the drain are located on the same side of the active layer.

6. The field effect transistor of claim 1 . wherein the gate is located on one side of the active layer, and the source and the drain are located on the opposite side of the active laver.

7. The field effect transistor of claim 1 , wherein the first and second metal oxide semiconductor layers are amorphous.

8. The field effect transistor of claim 1 , wherein the gate directly contacts the substrate.

9. The field effect transistor of claim 1 , wherein the source and the drain directly contact the gate insulating layer.

Assignees

• E Ink Holdings Inc

Inventors

• Zan Hsiao-Wen
• Liao Chun-Hung

Classifications

• H10D62/82

  Heterojunctions · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6756 Primary

  Amorphous oxide semiconductors · CPC title

• H01L29/267

  Electricity · mapped topic

• H01L29/78693 Primary

  Electricity · mapped topic