Semiconductor device having a diffusion region

Patent metadata

Field	Value
Publication number	US-9236460-B2
Application number	US-201313896305-A
Country	US
Kind code	B2
Filing date	May 16, 2013
Priority date	May 21, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A semiconductor device is disclosed. The semiconductor device is capable of obtaining a high reverse recovery resistant amount by allowing sheet resistance of a peripheral portion in a p type diffusion region that is in contact with a metal electrode through an insulating film on a surface to be as high as possible and reducing an increase in cost if possible. The semiconductor device includes: a p type diffusion region that is disposed in a surface layer of the one main surface of an n type semiconductor substrate; and a voltage-resistant region that surrounds the p type diffusion region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first-conductivity-type semiconductor substrate;
a second-conductivity-type diffusion region having a rectangular plane pattern that is disposed in a surface layer of one main surface of the first-conductivity-type semiconductor substrate; and
a ring-shaped voltage-resistant region that surrounds the second-conductivity-type diffusion region,
wherein the second-conductivity-type diffusion region includes:
an active region in which a metal electrode is in ohmic contact with a surface of a central portion thereof, and
a ring-shaped peripheral portion that surrounds the active region, that has an inner circumferential end and an outer circumferential end, and that includes an insulating film on a surface thereof; and

wherein the ring-shaped peripheral portion includes a second-conductivity-type diffusion region extension portion that is selectively diffused, that increases sheet resistance between the inner circumferential end and the outer circumferential end of the ring-shaped peripheral portion, and that includes:
a plurality of second-conductivity-type stretch-out portions that are stretched out from the inner circumferential end toward the outer circumferential end in a stripe shape having a predetermined width, that extend in an outer peripheral direction and maintain the predetermined width, that connect to the diffusion region, and that have a depth and an impurity concentration that are the same as that of the diffusion region; and
a ladder-shaped extension portion where a plurality of first-conductivity-type stripe-shaped substrate surfaces that are configured with exposed surfaces of the semiconductor substrate are alternately disposed in parallel to each other.

2. The semiconductor device according to claim 1 , wherein the second-conductivity-type stretch-out portion has short side having a width and the first-conductivity-type stripe-shaped substrate surface has a short side having a width, and wherein a ratio of the width of the short side of the second-conductivity-type stretch-out portion to the width of the short side of the first-conductivity-type stripe-shaped substrate surface is 0.1 or more and 0.5 or less.

3. The semiconductor device according to claim 1 , wherein, when the second-conductivity-type diffusion region has a diffusion depth defined by Xj and the first-conductivity-type stripe-shaped substrate surface has a short side having a width defined by L, L is larger than 1.6 multiplied by Xj.

4. The semiconductor device according to claim 1 , further comprising an insulating film that covers a surface of the ring-shaped peripheral portion.

5. The semiconductor device according to claim 1 , further comprising a separated electrode that is in ohmic contact with a surface of the ring-shaped peripheral portion and is electrically separated from the metal electrode.

6. The semiconductor device according to claim 1 , wherein the ladder-shaped extension portion has an outer circumference side, and wherein a plurality of second-conductivity-type ring-shaped diffusion regions are provided, that are electrically connected to the second-conductivity-type stretch-out portions and that have a diffusion depth larger than that of the second-conductivity-type diffusion region, and are separated from each other at the outer circumference side of the ladder-shaped extension portion.

7. The semiconductor device according to claim 6 , wherein the plurality of second-conductivity-type ring-shaped diffusion regions have an innermost circumferential end, the second-conductivity-type diffusion region has an outer circumferential end, and the second-conductivity-type stretch-out portion has an outer-circumferential-direction length, and wherein an interval in a predetermined direction between the innermost circumferential end of the plurality of second-conductivity-type ring-shaped diffusion regions and the outer circumferential end of the second-conductivity-type diffusion region is equal to or larger than the outer-circumferential-direction length of the second-conductivity-type stretch-out portion.

8. The semiconductor device according to claim 6 , wherein the plurality of second-conductivity-type ring-shaped diffusion regions have innermost circumferential ends, and wherein the second-conductivity-type stretch-out portions and the innermost circumferential ends of the plurality of second-conductivity-type ring-shaped diffusion regions are in contact with each other.

9. The semiconductor device according to claim 6 , wherein the second-conductivity-type ring-shaped diffusion region has a surface that is separated at an outer side of the ladder-shaped extension portion, and the semiconductor device further comprises a separated electrode that is electrically connected to a surface of the second-conductivity-type stretch-out portion and is provided at the surface of the second-conductivity-type ring-shaped diffusion region that is separated at an outer side of the ladder-shaped extension portion.

10. The semiconductor device according to claim 1 , wherein the active region has a side having an inner circumferential end having a shape, and the shape of the inner circumferential end in the side of the active region of the insulating film on the surface of the ring-shaped peripheral portion is a non-straight-line shape where an overhang length to the side of the active region is set to be large in a large-current portion and the overhang length is set to be small in a small-current portion according to an inner-circumferential-end plane distribution of the reverse recovery current having the peripheral portion as a path.

11. The semiconductor device according to claim 10 , wherein the second-conductivity-type diffusion region extension portion of the ring-shaped peripheral portion includes:
a plurality of first second-conductivity-type lattice line portions, each of which has an angle θ of 0° or more and 90° or less with respect to a direction from a center of the semiconductor device having a rectangular shape toward an outer circumferential end of the semiconductor device; and
a plurality of second second-conductivity-type lattice line portions, each of which has an angle of −θ with respect to the direction from the center toward the outer circumferential end of the semiconductor device, and the first second-conductivity-type lattice line portions and the second second-conductivity-type lattice line portions intersect each other at an angle of 2θ.

12. The semiconductor device according to claim 1 , wherein:
the second-conductivity-type diffusion region is an anode diffusion region; and
a first-conductivity-type cathode diffusion region having a concentration that is higher than that of the first-conductivity-type semiconductor substrate is installed on a surface layer of the other main surface of the first-conductivity-type semiconductor substrate, so that the semiconductor device has a function as a vertical diode.

13. The semiconductor device according to claim 1 , wherein:
the second-conductivity-type diffusion region is a second-conductivity-type base region that is selectively formed on a surface layer of the one main surface of the first-conductivity-type semiconductor substrate;
a first-conductivity-type source region is selectively formed on a surface of the base layer;
a gate electrode is formed to face surfaces of the first-conductivity-type semiconductor substrate, the base region, and the source region through a gate insulating film; and
a first-conductivity-type drain layer having a concentration that is higher than that of the first-conductivity-type semiconductor substrate is i

Assignees

• Fuji Electric Co Ltd

Inventors

• Koyama Hiromi
• Shiigi Takashi
• Fukuchi Akihiro
• Momota Seiji
• Matsui Toshiyuki

Classifications

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title