Wafer dicing with etch chamber shield ring for film frame wafer applications

Patent metadata

Field	Value
Publication number	US-9236305-B2
Application number	US-201414158529-A
Country	US
Kind code	B2
Filing date	Jan 17, 2014
Priority date	Jan 25, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.

First claim

What is claimed is:

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
coupling the semiconductor wafer to a film frame;
forming a mask above the semiconductor wafer, the mask covering and protecting the integrated circuits;
disposing the semiconductor wafer over a temperature controlled chuck surface of a plasma chamber and disposing the film frame over a top surface of a temperature controlled annular ring disposed around the temperature controlled chuck surface;
covering the film frame with a chamber shield ring without covering any portion of the semiconductor wafer with the chamber shield ring, wherein the chamber shield ring has an outer diameter greater than that of the film frame; and
plasma etching the semiconductor wafer while the semiconductor wafer is coupled to the film frame.

2. The method of claim 1 , further comprising:
cooling the temperature controlled chuck surface and the top surface of the temperature controlled annular ring.

3. The method of claim 2 , wherein cooling the temperature controlled chuck surface and the top surface of the temperature controlled annular ring comprises cooling the chuck surface and the top surface of the annular ring to less than 0 ° C.

4. The method of claim 2 , wherein cooling the temperature controlled chuck surface comprises supplying a gas through the temperature controlled chuck surface to a backside of the semiconductor wafer while plasma etching the semiconductor wafer.

5. The method of claim 4 , wherein supplying the gas through the temperature controlled chuck surface comprises providing a flow rate sufficient to maintain a backside pressure no greater than 3 mT.

6. The method of claim 1 , further comprising, prior to the plasma etching:
patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits; and
transferring the semiconductor wafer coupled to the film frame to a plasma etch chamber;
wherein plasma etching the semiconductor wafer comprises plasma etching the semiconductor wafer through the gaps in the patterned mask to form singulated integrated circuits while the semiconductor wafer is coupled to the film frame.

7. The method of claim 1 , wherein the shield ring is affixed to the plasma etch chamber by a set of lifter pins configured to raise and lower the shield ring between an elevated position and a lowered position.

8. The method of claim 1 , wherein the chamber shield ring is separated from a top surface of the film frame by a gap of 1 to 5 mm.

9. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
coupling the semiconductor wafer to a film frame, wherein a mask is disposed over the semiconductor wafer;
disposing the semiconductor wafer over a temperature controlled chuck surface of a plasma chamber and disposing the film frame over a top surface of a temperature controlled annular ring disposed around the temperature controlled chuck surface;
covering the film frame with a chamber shield ring without covering any portion of the semiconductor wafer with the chamber shield ring, wherein the chamber shield ring has an outer diameter greater than that of the film frame; and
plasma etching the semiconductor wafer while the semiconductor wafer is coupled to the film frame.

10. The method of claim 9 , further comprising:
cooling the temperature controlled chuck surface and the top surface of the temperature controlled annular ring.

11. The method of claim 10 , wherein cooling the temperature controlled chuck surface and the top surface of the temperature controlled annular ring comprises cooling the chuck surface and the top surface of the annular ring to less than 0 ° C.

12. The method of claim 10 , wherein cooling the temperature controlled chuck surface comprises supplying a gas through the temperature controlled chuck surface to a backside of the semiconductor wafer while plasma etching the semiconductor wafer.

13. The method of claim 12 , wherein supplying the gas through the temperature controlled chuck surface comprises providing a flow rate sufficient to maintain a backside pressure no greater than 3 mT.

14. The method of claim 9 , further comprising, prior to the plasma etching:
patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits; and
transferring the semiconductor wafer coupled to the film frame to a plasma etch chamber;
wherein plasma etching the semiconductor wafer comprises plasma etching the semiconductor wafer through the gaps in the patterned mask to form singulated integrated circuits while the semiconductor wafer is coupled to the film frame.

Assignees

• Applied Materials Inc

Inventors

• Lei Wei-Sheng
• Singh Saravjeet
• Dinev Jivko
• Iyer Aparna
• Eaton Brad
• Kumar Ajay

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P76/20

  of masks comprising organic materials · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title