Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)

Patent metadata

Field	Value
Publication number	US-9236292-B2
Application number	US-201314133262-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Dec 18, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

First claim

What is claimed is:

1. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
providing a previous layer metallization structure comprising an alternating metal line and dielectric line first grating pattern having a first direction;
forming a dielectric line second grating pattern above the previous layer metallization structure, the dielectric line second grating pattern having a second direction, perpendicular to the first direction;
forming a sacrificial structure above the first grating pattern and between the dielectric lines of the second grating pattern;
replacing portions of the sacrificial structure above and aligned with the metal lines of the first grating pattern with a first dielectric layer, and replacing portions of the sacrificial structure above and aligned with the dielectric lines of the first grating pattern with a second dielectric layer;
forming, by using a selective metal deposition process, one or more conductive vias in the first dielectric layer, on exposed portions of the metal lines of the first grating pattern;
recessing portions of the first and second dielectric layers; and
forming a plurality of metal lines in the recessed portions of the first and second dielectric layers, coupled with the one or more conductive vias, the plurality of metal lines having the second direction.

2. The method of claim 1 , wherein forming the one or more conductive vias by using the selective metal deposition process comprises using a precursor molecule possessing electron-acceptor ligands on a late transition metal center.

3. The method of claim 2 , wherein using the precursor molecule comprises using an N,N′-dialkyl-diazabutadiene metal precursor complex.

4. The method of claim 3 , wherein the N,N′-dialkyl-diazabutadiene metal precursor complex includes the late transition metal center selected from the group consisting of Mn, Cr, Fe, Co and Ni, and wherein the N,N′-dialkyl-diazabutadiene metal precursor complex has two N,N′-dialkyl-diazabutadiene ligands.

5. The method of claim 3 , wherein the N,N′-dialkyl-diazabutadiene metal precursor complex includes the late transition metal center selected from the group consisting of Ru, Mo and W, and wherein the N,N′-dialkyl-diazabutadiene metal precursor complex has three N,N′-dialkyl-diazabutadiene ligands.

6. The method of claim 1 , wherein forming the one or more conductive vias by using the selective metal deposition process comprises forming the one or more conductive vias at a temperature approximately in the range of 175-275 degrees Celsius.

7. The method of claim 1 , wherein a metal line of the plurality of metal lines in the recessed portions of the first and second dielectric layers is electrically coupled to a metal line of the previous layer metallization structure by one of the one or more conductive vias, the conductive via having a center directly aligned with a center of the metal line of the previous layer metallization structure and with a center of the metal line of the plurality of metal lines in the recessed portions of the first and second dielectric layers.

8. The method of claim 1 , wherein forming the first dielectric layer and the second dielectric layer comprises forming a different material for each layer, and wherein forming the one or more conductive vias is performed without deposition on exposed portions of the first dielectric layer and the second dielectric layer.

9. The method of claim 1 , wherein forming the first dielectric layer and the second dielectric layer comprises forming a same material for each layer, and wherein forming the one or more conductive vias is performed without deposition on exposed portions of the first dielectric layer and the second dielectric layer.

Assignees

• Romero Patricio E
• Clendenning Scott B
• Roberts Jeanette M
• Gstrein Florian
• Intel Corp

Inventors

• Romero Patricio E
• Clendenning Scott B
• Roberts Jeanette M
• Gstrein Florian

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• C23C16/45525

  Atomic layer deposition [ALD] · CPC title

• C23C16/18

  from metallo-organic compounds · CPC title

• C23C16/04

  Coating on selected surface areas, e.g. using masks · CPC title

• H10P14/432 Primary

  using selective deposition · CPC title