Sense amplifier scheme for low voltage SRAM and register files

Patent metadata

Field	Value
Publication number	US-9236114-B2
Application number	US-201414200602-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Feb 26, 2009
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.

First claim

What is claimed is:

1. A sense amplifier circuit comprising:
a bit line;
a sense amplifier output;
a keeper circuit coupled to the bit line, the keeper circuit including an NMOS transistor coupled between a power node and the bit line, wherein the keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line; and
a noise threshold control circuit connected to the sense amplifier output and the bit line, wherein the noise threshold control circuit comprises an inverter.

2. The sense amplifier circuit of claim 1 , wherein a drain node of the NMOS transistor is coupled to the power node through a PMOS transistor.

3. The sense amplifier circuit of claim 1 , wherein a gate node of the NMOS transistor is coupled to the power node.

4. The sense amplifier circuit of claim 3 , wherein the gate node of the NMOS transistor is coupled to the power node through a PMOS transistor.

5. The sense amplifier circuit of claim 1 , wherein a source node of the NMOS transistor is coupled to the bit line through a PMOS transistor.

6. The sense amplifier circuit of claim 1 , wherein a gate node of the NMOS transistor is coupled to a source node of the NMOS transistor.

7. The sense amplifier circuit of claim 1 , wherein the gate node of the PMOS transistor is coupled to the sense amplifier output.

8. The sense amplifier circuit of claim 1 , wherein the inverter comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit.

9. The sense amplifier circuit of claim 1 , further comprising a PMOS transistor, wherein a beta ratio of a PMOS transistor gate width to an NMOS transistor gate width is about 3.3.

10. A sense amplifier circuit comprising:
a bit line;
a sense amplifier output;
a keeper circuit coupled to the bit line, the keeper circuit including a first NMOS transistor coupled between a first power node and bit line, wherein the keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line;
an inverter having an input node coupled to the bit line and an output node coupled to the sense amplifier output; and
a noise threshold control circuit connected to the sense amplifier output, wherein the noise threshold control circuit is configured to have greater driving capability to pull a voltage level of the sense amplifier output toward that of a second power node than to pull the voltage level of the sense amplifier output toward that of the first power node.

11. The sense amplifier circuit of claim 10 , wherein the noise threshold control circuit comprises:
a second NMOS transistor coupled between the sense amplifier output and the second power node, the second NMOS transistor being configured to be turned off or on in response to a voltage level at the sense amplifier output; and
a third NMOS transistor coupled between the second NMOS transistor and the second power node, and a gate of the third NMOS transistor is coupled to the keeper circuit.

12. The sense amplifier circuit of claim 11 , wherein the first NMOS transistor is coupled to the first power node through a PMOS transistor, and the gate of the third NMOS transistor is coupled to the drain of the PMOS transistor.

13. The sense amplifier circuit of claim 10 , wherein a gate node of the first NMOS transistor is coupled to the first power node.

14. The sense amplifier circuit of claim 10 , wherein the gate node of the PMOS transistor is coupled to the sense amplifier output.

15. A sense amplifier circuit comprising:
a data line;
a sense amplifier output;
a keeper circuit comprising a first transistor and a second transistor connected in series and coupled between a first power node and the data line, a gate of the first transistor is coupled to the sense amplifier output; and
a noise resistant inverter, resistant to high state and low state noise on the data line, the noise resistant inverter comprising an input node coupled to the data line and an output node coupled to the sense amplifier output, wherein the noise resistant inverter is configured to have greater driving capability to pull a voltage level of the sense amplifier output toward that of a second power node than to pull the voltage level of the sense amplifier output toward that of the first power node.

16. The sense amplifier circuit of claim 15 , wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

17. The sense amplifier circuit of claim 16 , wherein a source of the first transistor is connected to the first power node, a drain of the first transistor is connected to a drain of the second transistor, and a source of the second transistor is connected to the data line.

18. The sense amplifier circuit of claim 17 , wherein a gate of the second transistor is connected to the drain of the second transistor.

19. The sense amplifier circuit of claim 16 , wherein a drain and a gate of the second transistor is connected to the first power node, a source of the second transistor is connected to a source of the first transistor, and a drain of the first transistor is connected to the data line.

20. The sense amplifier circuit of claim 16 , wherein a beta ratio of a gate width of the PMOS transistor to a gate width of the NMOS transistor is about 3.3.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Upputuri Bharath

Classifications

• G11C11/418

  Address circuits · CPC title

• G11C7/067 Primary

  Single-ended amplifiers · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title