Polishing method, polishing apparatus and GaN wafer

US9233449B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9233449-B2
Application numberUS-201013138635-A
CountryUS
Kind codeB2
Filing dateMar 19, 2010
Priority dateMar 27, 2009
Publication dateJan 12, 2016
Grant dateJan 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A polishing method can process and flatten, in a practical processing time and with high surface accuracy, a surface of a substrate of a Ga element-containing compound semiconductor. The polishing method includes: bringing a Ga element-containing compound semiconductor substrate ( 16 ) into contact with a polishing tool ( 10 ) in the presence of a processing solution ( 14 ) comprising a neutral pH buffer solution containing Ga ions; irradiating a surface of the substrate with light or applying a bias potential to the substrate, or applying a bias potential to the substrate while irradiating the surface of the substrate with light, thereby forming Ga oxide ( 16 a ) on the surface of the substrate; and simultaneously moving the substrate and the polishing tool relative to each other to polish and remove the Ga oxide formed on the surface of the substrate.

First claim

Opening claim text (preview).

The invention claimed is: 1. A polishing method comprising: preparing a Ga element-containing compound semiconductor substrate, whose surface has raised portions and recessed portions; immersing the substrate in a processing solution comprising a buffer solution containing Ga ions, a concentration of the Ga ions being in a range of 10 ppm to 100 ppm, and the buffer solution having a pH in a range of 6 to 8; irradiating the surface of the substrate with light or applying a bias potential to the substrate, or applying a bias potential to the substrate while irradiating the surface of the substrate with light, thereby forming Ga oxide on the surface of the substrate in the processing solution; and rotating the substrate and a polishing tool with respect to each other to selectively polish and remove the Ga oxide formed on the raised portions of the surface of the substrate, wherein the processing solution contains oxygen dissolved therein, and wherein the processing solution does not comprise nitrogen dissolved from any Ga element-containing compound semiconductor substrate. 2. The polishing method according to claim 1 , wherein the polishing tool has an acidic or basic solid catalyst at least in a surface area which comes into contact with or close to the substrate. 3. The polishing method according to claim 1 , wherein the processing solution further comprises metal oxide particles, diamond particles, or catalyst particles whose surfaces are modified with an acidic or basic functional group, or a mixture of these particles. 4. The polishing method according to claim 1 , wherein the processing solution further comprises an oxidizing agent. 5. The polishing method according to claim 1 , wherein at least a surface area of the polishing tool, which comes into contact with or close to the substrate, has been conditioned to have desired flatness and appropriate roughness. 6. The polishing method according to claim 1 , further comprising: preparing the processing solution prior to immersing the substrate in the processing solution.

Assignees

Inventors

Classifications

  • taking regard of the pH-value of lapping agents · CPC title

  • H10P52/00Primary

    Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

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What does patent US9233449B2 cover?
A polishing method can process and flatten, in a practical processing time and with high surface accuracy, a surface of a substrate of a Ga element-containing compound semiconductor. The polishing method includes: bringing a Ga element-containing compound semiconductor substrate ( 16 ) into contact with a polishing tool ( 10 ) in the presence of a processing solution ( 14 ) comprising a neutral…
Who is the assignee on this patent?
Sano Yasuhisa, Yamauchi Kazuto, Murata Junji, and 4 more
What technology area does this patent fall under?
Primary CPC classification B24B37/0056. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jan 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).