Resonant clock amplifier with a digitally tunable delay

Patent metadata

Field	Value
Publication number	US-9231571-B2
Application number	US-201314080733-A
Country	US
Kind code	B2
Filing date	Nov 14, 2013
Priority date	Aug 20, 2010
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

First claim

What is claimed is:

1. A device comprising:
a clock circuit comprising amplifiers, at least one of the amplifiers being a resonant amplifier, the clock circuit being configured to produce amplified clock signals derived from a source clock signal, wherein the amplified clock signals comprise at least one amplified and programmably delayed clock signal;
a first circuit configured to latch an input data stream using a first amplified clock signal produced by the clock circuit, the first amplified clock signal having a first frequency; and
a second circuit that is electrically coupled to the first circuit, the second circuit configured to demultiplex the data stream latched by the first circuit using at least a second amplified clock signal produced by the clock circuit, the second amplified clock signal having a second frequency that is less than the first frequency.

2. The device of claim 1 , wherein the second amplified clock signal comprises the at least one amplified and programmably delayed clock signal and the first frequency is equivalent to a source frequency of the source clock signal.

3. The device of claim 1 , wherein the clock circuit is configured to adjust a delay associated with the at least one amplified and programmably delayed clock signal by adjusting a capacitance.

4. The device of claim 1 , wherein the clock circuit is configured to adjust a delay associated with the at least one amplified and programmably delayed clock signal when a source frequency of the source clock signal changes.

5. The device of claim 1 , wherein the resonant amplifier is associated with a tunable delay element.

6. The device of claim 5 , wherein the clock circuit is configured to adjust a delay associated with the at least one amplified and programmably delayed clock signal by adjusting the tunable delay element.

7. The device of claim 6 , wherein the tunable delay element comprises a variable capacitor that is adjustable by an analog control signal.

8. The device of claim 7 , further comprising:
a calibration circuit that is configured to generate the analog control signal.

9. The device of claim 1 , further comprising:
a clock and data recovery (CDR) circuit that is configured to adjust a phase of the first amplified clock signal.

10. The device of claim 1 , wherein the clock circuit comprises at least one of a phase interpolator, a VCO, or a LC-tank circuit.

11. The device of claim 1 , wherein the resonant amplifier comprises:
an input pair of transistors, each having a source, a gate, and a drain, wherein the sources of the input pair of transistors are coupled to each other and to ground, the gates are configured to receive an input clock signal at the second frequency that less than the first frequency, and the drains are configured to output the second amplified clock signal to drive a capacitive load;
an inductor coupled between the drains of the of the input transistors; and
a resistor, coupled between the inductor and a power supply.

12. The device of claim 11 , wherein the resonant amplifier further comprises:
a first pair of delay elements, coupled to the drains of the input pair of transistors by a respective first pair of coupling transistors and configured to delay output of the amplified clock signal when the first pair of coupling transistors receive a control signal to couple the first pair of delay elements to the drains of the input pair of transistors.

13. The device of claim 12 , wherein the first pair of delay elements comprise a first pair of capacitors.

14. The device of claim 12 , wherein the resonant amplifier further comprises:
a second pair of delay elements, coupled to the drains of the input pair of transistors by a respective second pair of coupling transistors and configured to independently delay output of the second amplified clock signal when the second pair of coupling transistors receive the control signal to couple the second pair of delay elements to the drains of the input pair of transistors.

15. The device of claim 1 , wherein the first circuit comprises a slicer circuit and the second circuit comprises a demultiplexer circuit.

16. A device comprising:
a clock circuit comprising amplifiers, at least one of the amplifiers being a resonant amplifier, the clock circuit being configured to produce amplified clock signals derived from a source clock signal, wherein the amplified clock signals comprise at least one amplified and programmably delayed clock signal;
a first circuit configured to multiplex a plurality of data signals using a first amplified clock signal produced by the clock circuit to generate a multiplexed data signal, the first amplified clock signal having a first frequency; and
a second circuit configured to latch the multiplexed data signal using a second amplified clock signal produced by the clock circuit independently of the first amplified clock signal, the second amplified clock signal having a second frequency.

17. The device of claim 16 , wherein the second frequency is greater than the first frequency.

18. The device of claim 16 , wherein the resonant amplifier is associated with a tunable delay element and the clock circuit is configured to adjust a delay associated with the at least one amplified and programmably delayed clock signal by adjusting the tunable delay element.

19. A method comprising:
latching an input data stream at a first circuit driven by a first amplified clock signal produced by a first resonant amplifier amplifying a first clock signal derived from a clock source at a first frequency;
receiving the input data stream latched by the first circuit at a second circuit driven by at least a second amplified clock signal produced by a second resonant amplifier amplifying a second clock signal derived from the clock source at a second frequency that is less than the first frequency, wherein the at least one of the first or second resonant amplifiers is configured to amplify and programmably delay the first or second clock signals, respectively; and
programmably adjusting a delay of the first or second clock signals when a source frequency of the clock source changes.

20. The method of claim 19 , wherein the second frequency is less than the first frequency.

Assignees

• Broadcom Corp

Inventors

• Raghavan Bharath
• Cao Jun
• Momtaz Afshin

Classifications

• H03K5/07 Primary

  by the use of resonant circuits · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03K2005/00208

  using differential stages · CPC title

• H04L7/027

  extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit · CPC title