Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9231029-B2
Application number	US-201414284516-A
Country	US
Kind code	B2
Filing date	May 22, 2014
Priority date	Dec 18, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

According to one embodiment, a semiconductor memory device includes a plurality of global bit lines, a plurality of word lines, a plurality of bit lines, a plurality of resistance change films, a plurality of semiconductor layers, a gate insulating film, and a plurality of gate electrodes. Spacing in the first direction between the plurality of semiconductor layers is larger than spacing in the second direction between the plurality of semiconductor layers. The plurality of gate electrodes is separated in the first direction.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of global bit lines extending in a first direction and arranged with spacings in a second direction crossing the first direction;
a plurality of word lines spaced in the first direction, extending in the second direction, and stacked via an interlayer insulating layer in a third direction crossing the first direction and the second direction, the word lines including a first word line and a second word line arranged adjacently to each other in the first direction;
a plurality of bit lines arranged with spacings in the second direction between the word lines, and extending in the third direction, the bit lines including a first bit line and a second bit line arranged adjacently to each other in the first direction, the first bit line provided between the first word line and the second word line, the first word line provided between the first bit line and the second bit line;
a plurality of resistance change films provided between the word lines and the bit lines, the resistance change films including a first resistance change film and a second resistance change film arranged adjacently to each other in the first direction, the first word line provided between the first bit line via the first resistance change film and the second bit line via the second resistance change film;
a plurality of semiconductor layers provided between the global bit lines and the bit lines;
a gate insulating film provided on a side surface of the semiconductor layers; and
a plurality of gate electrodes provided via the gate insulating film between the semiconductor layers in the second direction and on the side surface of the semiconductor layers in the first direction, and extending in the second direction,
spacing in the first direction between the plurality of semiconductor layers being larger than spacing in the second direction between the plurality of semiconductor layers,
the plurality of gate electrodes being separated in the first direction, and
in the first direction, a distance between the gate electrodes adjacently arranged being shorter than a distance between the first bit line and the second bit line.

2. The device according to claim 1 , wherein pitch in the first direction of the plurality of semiconductor layers adjacently arranged is larger than pitch in the second direction of the plurality of semiconductor layers adjacently arranged.

3. The device according to claim 1 , wherein a contact is provided in an end part in the second direction of the gate electrodes, and the contact extends further downward than the gate electrodes in the third direction.

4. The device according to claim 3 , wherein the global bit lines are not provided below the end part in the second direction of the gate electrode.

5. The device according to claim 3 , wherein the gate electrodes have first end parts and second end parts opposite to the first end parts in the second direction, the gate electrodes include a first gate electrode and a second gate electrode arranged adjacently to each other in the first direction, the contact includes a first contact and a second contact, the first contact is in contact with a first end part of the first gate electrode, and the second contact is in contact with a second end part of the second gate electrode.

6. The device according to claim 5 , wherein the first end part of the first gate electrode is projected further in the second direction than a first end part of the second gate electrode not provided with the contact.

7. The device according to claim 1 , wherein
the semiconductor layers are shaped like a column, and
the gate insulating film is provided on a first side surface facing the first direction and a second side surface facing the second direction of the semiconductor layers.

8. The device according to claim 1 , wherein the spacing between the semiconductor layers in the second direction is smaller than sum of twice film thickness of the gate insulating film and twice film thickness of the gate electrodes.

9. The device according to claim 1 , wherein the spacing between the semiconductor layers in the first direction is larger than sum of twice film thickness of the gate insulating film and twice film thickness of the gate electrodes.

10. The device according to claim 1 , wherein the gate electrodes are extracted longer than a film thickness of the gate electrodes in the second direction.

11. The device according to claim 1 , further comprising:
an end pattern adjacent to a first semiconductor layer in the second direction, the end pattern placed at an end in the second direction of the plurality of semiconductor layers,
wherein a part of the gate electrodes is placed between the end pattern and the first semiconductor layer.

12. The device according to claim 11 , further comprising:
an insulating film provided on a side surface of the end pattern,
wherein distance between the end pattern and the first semiconductor layer is smaller than sum of twice film thickness of the gate insulating film and twice film thickness of the gate electrodes.

13. The device according to claim 11 , further comprising:
an insulating film provided on a side surface of the end pattern,
wherein the insulating film is made of same material as the gate insulating film, and
the part of the gate electrodes is provided on the side surface of the end pattern via the insulating film.

14. The device according to claim 11 , wherein the end pattern extends in the second direction.

15. The device according to claim 11 , wherein a contact is in contact with the end pattern.

Assignees

• Toshiba Kk

Inventors

• Murooka Kenichi

Classifications

• H01L27/2481 Primary

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title