FinFETs having dielectric punch-through stoppers

Patent metadata

Field	Value
Publication number	US-9230959-B2
Application number	US-201113314942-A
Country	US
Kind code	B2
Filing date	Dec 8, 2011
Priority date	May 6, 2008
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

First claim

What is claimed is:

1. A method comprising:
forming an isolation region in a semiconductor substrate, wherein an active region of the semiconductor substrate is located between opposite sidewalls of the isolation region;
recessing the isolation region to expose sidewalls of the active region;
masking the exposed sidewalls of the active region;
after masking the exposed sidewalls, recessing the isolation region to expose an intermediate portion of the active region; and
after recessing the isolation region to expose the intermediate portion, oxidizing the intermediate portion of the active region to form an insulator layer, wherein the insulator layer is disposed between a top portion of the active region and a bottom portion of the active region, and wherein the intermediate portion is at a level between a top surface and a bottom surface of the isolation region.

2. The method of claim 1 , wherein the step of masking the exposed sidewalls comprises forming a cap to mask the exposed sidewalls, the exposed sidewalls being sidewalls of the top portion of the active region, with the cap contacting the sidewalls of the top portion of the active region, after the step of recessing the isolation region to expose the intermediate portion, portions of the sidewalls of the active region unmasked by the cap are exposed, and the step of oxidizing the intermediate portion comprises oxidizing the exposed portions of the sidewalls of the active region unmasked by the cap to form the insulator layer.

3. The method of claim 1 , wherein the step of recessing the isolation region to expose the intermediate portion comprises isotropic etching.

4. The method of claim 1 , wherein the step of recessing the isolation region to expose sidewalls of the active region is performed using a photoresist as an etching mask.

5. The method of claim 1 , wherein the step of recessing the isolation region to expose sidewalls of the active region is performed without using a photoresist using an etching mask.

6. A method comprising:
forming an isolation region in a semiconductor substrate, wherein an active region of the semiconductor substrate is located between opposite sidewalls of the isolation region;
recessing the isolation region to expose sidewalls of the active region;
after recessing the isolation region to expose sidewalls of the active region, blanket forming a mask layer;
removing a joint portion between a vertical portion and a horizontal portion of the mask layer to form an opening, wherein the vertical portion of the mask layer is on a sidewall of the active region; and
after the removing the joint portion, oxidizing an intermediate portion of the active region to form an insulator layer, wherein the insulator layer is disposed between a top portion of the active region and a bottom portion of the active region, and wherein the intermediate portion is at a level between a top surface and a bottom surface of the isolation region.

7. The method of claim 6 further comprising, before the step of oxidizing the intermediate portion of the active region, implanting oxygen ions into the intermediate portion of the active region through the opening.

8. The method of claim 1 , wherein a bottom of the insulator layer is higher than a bottom surface of the isolation region.

9. A method comprising:
forming an isolation region on a semiconductor substrate, wherein the isolation region has a first height, and wherein the isolation region defines an active region in the semiconductor substrate;
recessing the isolation region to expose a first portion of a sidewall of the active region;
forming a hard mask on the first portion of the sidewall of the active region, wherein a portion of the isolation region is exposed through the hard mask;
recessing the exposed portion of the isolation region to expose a second portion of the sidewall of the active region below the hard mask; and
oxidizing the second portion of the sidewall of the active region below the hard mask to form an insulator layer fully isolating an upper portion of the active region from an underlying portion of the semiconductor substrate.

10. The method of claim 9 , wherein the insulator layer has a second height, and wherein a ratio of the first height to the second height is between about 1.4 and about 30.

11. The method of claim 9 , wherein the insulator layer has a width between about two times to about three times a width of the active region.

12. The method of claim 9 , wherein the insulator layer has a height between about 10 nm and about 70 nm.

13. The method of claim 9 further comprising, when the step of oxidizing the second portion of the sidewall of the active region is performed, simultaneously oxidizing exposed portions of sidewalls of an additional active region, wherein a width of the additional active region is greater than a width of the active region, and wherein after the step of oxidizing the exposed portions of the sidewalls of the additional active region, oxide regions formed from opposite sidewalls of the additional active region are spaced apart from each other by a portion of the additional active region not oxidized.

14. The method of claim 9 further comprising, after the step of oxidizing the second portion of the sidewall of the active region, forming a FinFET using the upper portion of the active region as a fin.

15. A method comprising:
providing a semiconductor substrate comprising a planar device region and a FinFET region;
forming isolation regions, wherein the isolation regions define a first active region in the planar device region and a second active region in the FinFET region;
performing a first recessing on the isolation regions to expose first portions of sidewalls of the second active region;
forming a hard mask on the first portions of the sidewalls of the second active region;
after forming the hard mask, performing a second recessing on portions of the plurality of isolation regions exposed through the hard mask to expose second portions of the sidewalls of the second active region that are below the hard mask; and
after performing the second recessing, oxidizing the second portions of the sidewalls of the second active region to form an insulator layer, wherein the insulator layer isolates a top portion of the second active region from the semiconductor substrate.

16. The method of claim 15 , wherein the first recessing comprises forming a mask to cover the first active region and portions of the plurality of isolation regions on opposite sides of the first active region.

17. The method of claim 15 , wherein no photoresist is formed for the step of the first recessing, and wherein sidewalls of the first active region are exposed after the second recessing.

18. The method of claim 17 , wherein during the step of oxidizing the second portions of the sidewalls of the second active region, under-cut oxidation regions are formed on sidewalls of the first active region, wherein the under-cut oxidation regions extends partially into the first active region.

19. The method of claim 15 further comprising, before the step of forming the hard mask and after the step of the first recessing, forming a buffer oxide on a top and the sidewalls of the second active region.

Assignees

• Chang Cheng-Hung
• Yu Chen-Hua
• Yeh Chen-Nan
• Taiwan Semiconductor Mfg

Inventors

• Chang Cheng-Hung
• Yu Chen-Hua
• Yeh Chen-Nan

Classifications

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0128 Primary

  Manufacturing their channels · CPC title