Techniques and configurations associated with a capductor assembly

Patent metadata

Field	Value
Publication number	US-9230944-B1
Application number	US-201414464484-A
Country	US
Kind code	B1
Filing date	Aug 20, 2014
Priority date	Aug 20, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC) assembly comprising:
a semiconductor wafer;
a plurality of inductors disposed on a first side of the semiconductor wafer, wherein the plurality of inductors are at least partially embedded in electrically insulative material;
a first plurality of interconnect structures disposed on a surface of the electrically insulative material, wherein the plurality of interconnect structures are electrically coupled to the plurality of inductors and configured to electrically couple the plurality of inductors to a die;
a plurality of capacitors disposed on a second side of the wafer, the second side of the wafer disposed opposite the first side of the wafer, wherein the plurality of capacitors are electrically coupled with a second plurality of interconnect structures that are configured to electrically couple the plurality of capacitors with the die.

2. The IC assembly of claim 1 , wherein the plurality of inductors are selected from a group consisting of: magnetic core inductors (MCIs) or air core inductors (ACIs).

3. The IC assembly of claim 1 , wherein the plurality of capacitors are disposed on an adhesive layer that physically couples the capacitors with the wafer.

4. The IC assembly of claim 3 , wherein the plurality of capacitors comprise discrete ceramic capacitors and the second plurality of interconnect structures comprise metallic terminals of the discrete ceramic capacitors.

5. The IC assembly of claim 1 , wherein the electrically insulative material is a first electrically insulative material, and wherein the plurality of capacitors comprises metal-insulator-metal (MIM) capacitors, and wherein the second plurality of interconnect structures is disposed in a surface of a second electrically insulative material that is disposed over the plurality of capacitors.

6. The IC assembly of claim 1 , wherein the die is a processor.

7. A method of forming a module comprising:
providing a wafer;
forming a plurality of inductors on a first side of the wafer;
depositing an electrically insulative material over the plurality of inductors to at least partially embed the inductors in the electrically insulative material;
forming a first plurality of interconnect structures on a surface of the electrically insulative material, wherein the first plurality of interconnect structures are electrically coupled to the plurality of inductors, and wherein the first plurality of interconnect structures are configured to electrically couple the plurality of inductors to a die;
forming a plurality of capacitors on a second side of the wafer, wherein the second side of the wafer is disposed opposite the first side of the wafer, and wherein the plurality of capacitors have a second plurality of interconnect structures formed on the plurality of capacitors to electrically couple the plurality of capacitors to the die.

8. The method of claim 7 , wherein the plurality of inductors is selected from a group consisting of: magnetic core inductors (MCIs) or air core inductors (ACIs).

9. The method of claim 7 , wherein forming the plurality of capacitors on the second side of the wafer further comprises:
depositing an adhesive layer on the second side of the wafer; and
depositing the plurality of capacitors onto the adhesive layer.

10. The method of claim 9 , wherein the plurality of capacitors are discrete ceramic capacitors and the second plurality of interconnect structures are metallic terminals of the discrete ceramic capacitors.

11. The method of claim 7 , wherein the electrically insulative material is a first electrically insulative material, and wherein forming the plurality of capacitors on the second side of the wafer further comprises:
forming a plurality of metal-insulator-metal (MIM) capacitors on the second side of the wafer;
depositing a second electrically insulative material over the MIM capacitors to at least partially embed the MIM capacitors in the second electrically insulative material; and
forming the second plurality of interconnect structures in a surface of the second electrically insulative material.

12. The method of claim 7 , wherein the wafer is a semiconductor wafer.

13. The method of claim 7 , wherein the die is a processor.

14. An apparatus comprising:
a plurality of build-up layers having a plurality of electrical routing features and an integrated circuit (IC) assembly embedded therein, wherein the IC assembly includes:
a plurality of inductors disposed on a first side of a semiconductor wafer and at least partially embedded in an electrically insulative material;
a first plurality of interconnect structures electrically coupled with the plurality of inductors and disposed on a surface of the electrically insulative material, wherein a first subset of the plurality of electrical routing features route electrical signals between the first plurality of interconnect structures and a side of the apparatus; and
a plurality of capacitors disposed on a second side of the wafer, the second side of the wafer disposed opposite the first side of the wafer, wherein the plurality of capacitors are electrically coupled with a second plurality of interconnect structures, and wherein a second subset of the plurality of electrical routing features route electrical signals between the second plurality of interconnect structures and the side of the apparatus.

15. The apparatus of claim 14 , wherein the plurality of inductors are selected from a group consisting of: magnetic core inductors (MCIs) or air core inductors (ACIs).

16. The apparatus of claim 14 , wherein the plurality of capacitors are disposed on an adhesive layer that physically couples the capacitors with the wafer.

17. The apparatus of claim 16 , wherein the plurality of capacitors comprise discrete ceramic capacitors and the second plurality of interconnect structures comprise metallic terminals of the discrete ceramic capacitors.

18. The apparatus of claim 14 , wherein the electrically insulative material is a first electrically insulative material, and wherein the plurality of capacitors comprises metal-insulator-metal (MIM) capacitors, and wherein the second plurality of interconnect structures is disposed in a surface of a second electrically insulative material that is disposed over the plurality of capacitors.

19. The apparatus of claim 14 , wherein the IC assembly is a passive portion of an integrated voltage regulator and further comprising an active voltage regulation circuit to regulate voltage provided to a die side of the package core, wherein the active voltage regulation circuit is electrically coupled with the IC assembly.

20. The apparatus of claim 14 , wherein the apparatus is a package assembly and the side of the apparatus is a die side of the package assembly.

21. The apparatus of claim 14 , wherein the apparatus is a motherboard.

22. A method of forming a package comprising:
providing a package core;
laser forming a cavity into the package core;
depositing into the cavity an assembly having a plurality of inductors disposed on a first side of a semiconductor wafer and a plurality of capacitors disposed on a second side, opposite the first side, of the semiconductor wafer;
depositing an encapsulation material over the assembly to embed the assembly into the package;
forming capacitor routing features to electrically couple the plurality of capacitors with a die side of the package core; and
forming inductor routing features to electrically

Assignees

• Intel Corp

Inventors

• Lambert William J
• Hill Michael J
• Radhakrishnan Kaladhar

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/073

  of die-attach connectors · CPC title