Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby

Patent metadata

Field	Value
Publication number	US-9230904-B2
Application number	US-201313973627-A
Country	US
Kind code	B2
Filing date	Aug 22, 2013
Priority date	Aug 22, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising an electrode structure including electrodes sequentially stacked on a substrate,
wherein each of the electrodes comprises:
a connecting portion horizontally protruding outward relative to a plane at which a sidewall of one of the electrodes located thereon, is disposed; and
an aligned portion having a sidewall that is coplanar with a sidewall of the one of the electrodes located thereon or another of the electrodes located thereunder,

wherein vertically adjacent at least two of the electrodes have sidewalls that are coplanar,
wherein the electrode structure comprises at least one first group and at least one second group, and each of the at least one first group and the at least one second group comprises plural ones of the electrodes that are stacked on the substrate along a direction perpendicular to a top surface of the substrate,
wherein the connecting portions of the electrodes of the at least one first group are positioned at a first side of the electrode structure and the aligned portions of the at least one first group are positioned at a second side of the electrode structure opposite to the first side of the electrode structure, and
the connecting portions of the electrodes of the at least one second group are positioned at the second side of the electrode structure and the aligned portions of the at least one second group are positioned at the first side of the electrode structure.

2. The device of claim 1 , wherein a number of the electrodes of each of the at least one first group and the at least one second group ranges from 2 to 16.

3. The device of claim 1 , wherein the at least one first group comprises even-numbered ones of the electrodes stacked on the substrate and the at least one second group comprises odd-numbered electrodes stacked on the substrate.

4. The device of claim 1 , wherein the at least one second group is disposed on or below the at least one first group.

5. The device of claim 1 , wherein the at least one first group comprises (4n+1)-th and (4n+2)-th ones of the electrodes stacked on the substrate and the at least one second group comprises (4n+3)-th and (4n+4)-th ones of the electrodes, and
wherein n is at least one selected from zero or natural numbers in such a way that (4n+4) is smaller a total stacking number of the electrodes.

6. The device of claim 1 , wherein the connecting and the aligned portions of each of the electrodes are positioned at both opposite end portions of corresponding electrode.

7. The device of claim 1 , wherein the electrode structure comprises a first region, a second region, and an array region interposed therebetween, and each of the connecting portions and the aligned portions is positioned on one of the first and the second regions.

8. The device of claim 7 , further comprising:
vertical patterns vertically penetrating the array region of the electrode structure; and
memory elements interposed between the vertical patterns and the electrodes.

9. The device of claim 8 , wherein the memory elements comprise a material or a layer structure configured to be able to store charges or exhibit a variable resistance property.

10. A three-dimensional semiconductor device comprising an electrode structure including electrodes sequentially stacked on a substrate,
wherein each of the electrodes comprises:
a connecting portion horizontally protruding outward relative to a plane at which a sidewall of one of the electrodes located thereon, is disposed; and
an aligned portion having a sidewall that is coplanar with a sidewall of the one of the electrodes located thereon or another of the electrodes located thereunder,

wherein vertically adjacent at least two of the electrodes have sidewalls that are coplanar,
wherein connecting portions of even-numbered ones of the electrodes are positioned at a first side of the electrode structure and the aligned portions of the even-numbered ones of the electrodes are positioned at a second side of the electrode structure opposite to the first side of the electrode structure, and
wherein connecting portions of odd-numbered ones of the electrodes are positioned at the second side of the electrode structure and the aligned portions of odd-numbered ones of the electrodes are positioned at the first side of the electrode structure.

11. A three-dimensional semiconductor device comprising an electrode structure including electrodes sequentially stacked on a substrate,
wherein each of the electrodes comprises:
a connecting portion horizontally protruding outward relative to a plane at which a sidewall of one of the electrodes located thereon, is disposed; and
an aligned portion having a sidewall that is coplanar with a sidewall of the one of the electrodes located thereon or another of the electrodes located thereunder, and

wherein at least one dummy pattern is spaced apart horizontally from one of electrodes and is formed of the same material as the one of the electrodes.

12. The device of claim 11 , wherein the at least one dummy pattern is in an electrical floating state.

13. A three-dimensional semiconductor device comprising an electrode structure including electrodes sequentially stacked on a substrate,
wherein each of the electrodes comprises:
a connecting portion horizontally protruding outward relative to a plane at which a sidewall of one of the electrodes located thereon, is disposed; and
an aligned portion having a sidewall that is coplanar with a sidewall of the one of the electrodes located thereon or another of the electrodes located thereunder,

wherein vertically adjacent at least two of the electrodes have sidewalls that are coplanar, and
wherein plugs are disposed on the electrode structure, and
wherein the electrode structure comprises:
a body portion including ones of the electrodes that are electrically connected to the plugs; and
a dummy portion including ones of the electrodes that are electrically separated from the plugs,
wherein the dummy portion is spaced apart horizontally from the body portion.

14. The device of claim 13 , wherein the body portion comprises at least one body sidewall portion, and the dummy portion comprises a first dummy sidewall portion facing the body sidewall portion,
wherein the body sidewall portion and the first dummy sidewall portion are disposed to have mirror symmetry to each other, and each of the body sidewall portion and the first dummy sidewall portion has a stepwise section.

15. The device of claim 14 , wherein the dummy portion further comprises a second dummy sidewall portion facing the first dummy sidewall portion, and
the second dummy sidewall portion is smaller than the first dummy sidewall portion, in terms of an angle with respect to a line normal to a top surface of the substrate.

16. The device of claim 15 , wherein the second dummy sidewall portion has a stepwise section.

17. The device of claim 13 , wherein the dummy portion includes plural ones of the electrodes that are consecutively stacked on the substrate.

Assignees

• Eun Dongseog
• Lee Young-Ho
• Lee Joonhee
• Lee Seok-Won
• Shin Yoocheol
• Samsung Electronics Co Ltd

Inventors

• Eun Dongseog
• Lee Young-Ho
• Lee Joonhee
• Lee Seok-Won
• Shin Yoocheol

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title