Process for fabricating a silicon-on-insulator structure

Patent metadata

Field	Value
Publication number	US-9230848-B2
Application number	US-201213629093-A
Country	US
Kind code	B2
Filing date	Sep 27, 2012
Priority date	Oct 3, 2011
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Embodiments of the invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s.

First claim

What is claimed is:

1. A method for fabricating a silicon-on-insulator structure comprising a silicon layer, a buried oxide layer having a thickness of 15 nm or less, and a support substrate, the method comprising:
providing a donor substrate comprising the silicon layer and the support substrate, only one of the donor substrate and the support substrate being covered with the oxide layer;
forming, in the donor substrate, a weak zone bounding the silicon layer;
plasma activating the oxide layer;
bonding the donor substrate to the support substrate using an oxide-to-silicon molecular bonding process, the oxide layer being located at the bonding interface and having a thickness of 15 nm or less, the bonding being carried out in a partial vacuum of between 0.1 mbar and 100 mbar in an atmosphere containing less than 100 ppm of water;
implementing a bond-strengthening anneal at a temperature of 350° C. or less, the bond-strengthening anneal causing the donor substrate to cleave along the weak zone; and
applying, to the silicon-on-insulator structure, a heat treatment for repairing defects at a temperature above 900° C., the transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment being achieved at a ramp rate above 10° C./s.

2. The method of claim 1 , further comprising carrying out the bonding in a partial vacuum of between 0.5 mbar and 10 mbar.

3. The method of claim 1 , further comprising performing the bond-strengthening anneal at a temperature between 300° C. and 350° C. for a time between 5 hours and 15 hours.

4. The method of claim 3 , wherein the silicon layer has a thickness of 600 nm or less.

5. The method of claim 4 , wherein the silicon layer has a thickness between 270 nm and 510 nm.

6. The method of claim 5 , wherein the silicon layer has a thickness equal to 330 nm.

7. The method of claim 1 , wherein the silicon layer has a thickness of 600 nm or less.

8. The method of claim 7 , wherein the silicon layer has a thickness between 270 nm and 510 nm.

9. The method of claim 8 , wherein the silicon layer has a thickness equal to 330 nm.

10. The method of claim 1 , further comprising performing the bond-strengthening anneal at a temperature between 300° C. and 350° C. for a time between 5 hours and 15 hours.

11. The method of claim 1 , further comprising using mechanical energy to cause the donor substrate to cleave along the weak zone.

12. The method of claim 1 , wherein plasma activating the oxide layer comprises using an oxygen plasma to activate the oxide layer.

13. The method of claim 1 , wherein forming the weak zone in the donor substrate comprises implanting atomic species into the donor substrate.

14. The method of claim 1 , wherein the buried oxide layer has a thickness less than 10 nm.

15. A silicon-on-insulator structure comprising a silicon layer, a buried oxide layer having a thickness of 15 nm or less, and a support substrate, wherein a defectivity of the structure in terms of defect clusters is 60 or less, and a bond strength between the buried oxide layer and the silicon layer or the support substrate at a bonding interface therebetween is at least about 600 mJ/m 2 .

16. A silicon-on-insulator structure as recited in claim 15 , wherein the silicon-on-insulator structure comprises a wafer having a diameter of about 300 mm.

17. A silicon-on-insulator structure as recited in claim 15 , wherein a thickness of the silicon layer is 50 nm or less.

18. A silicon-on-insulator structure as recited in claim 17 , wherein the thickness of the silicon layer is 20 nm or less.

19. A silicon-on-insulator structure as recited in claim 18 , wherein the thickness of the silicon layer is about 12 nm.

Assignees

• Soitec Silicon On Insulator

Inventors

• David Carole
• Kerdiles Sébastien

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title