Memory device having electrically floating body transitor

Patent metadata

Field	Value
Publication number	US-9230651-B2
Application number	US-201313746523-A
Country	US
Kind code	B2
Filing date	Jan 22, 2013
Priority date	Apr 8, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

First claim

That which is claimed is:

1. A semiconductor memory cell comprising:
a floating body region storing a charge or lack of charge indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a gate positioned between said first and second regions; and
a back-bias region configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;
wherein said back bias region has a lower band gap than said floating body region.

2. The semiconductor memory cell of claim 1 , further comprising a substrate region, wherein said back-bias region is positioned between said substrate region and said floating body region.

3. The semiconductor memory cell of claim 1 , wherein said floating body region comprises first and second subregions, wherein said first subregion has a first doping concentration level and said second region has a second doping concentration level, and wherein said first doping concentration is different from said second doping concentration level.

4. The semiconductor memory cell of claim 3 , wherein said first and second subregions have the same conductivity type.

5. The semiconductor memory cell of claim 3 , wherein said first subregion is further from said back-bias region than a distance from said second subregion to said back bias region, and wherein said second doping concentration level is greater than said first doping concentration level.

6. The semiconductor memory cell of claim 3 , wherein said floating body region further comprises a third subregion, said third subregion having a third doping concentration level, wherein said third doping concentration level is different from at least one of said first and second doping concentration levels.

7. The semiconductor memory cell of claim 6 , wherein said first subregion is furthest from said back-bias region, relative to said second and third subregions, and said first doping concentration level is lowest relative to said second and third doping concentration levels.

8. The semiconductor memory cell of claim 3 , wherein said first and second subregions are localized so that they do not underlie said first and second regions.

9. The semiconductor memory cell of claim 1 , further comprising at least one halo region adjacent to at least one of said first and second regions, wherein each said halo region comprise a first conductivity type selected from p-type conductivity type and n-type conductivity type; and wherein said first and second regions each comprise a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, wherein said second conductivity type is different from said first conductivity type.

10. The semiconductor memory cell of claim 1 , where said first and second states are stable states.

Assignees

• Widjaja Yuniarto
• Han Jin-Woo
• Louie Benjamin S
• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto
• Han Jin-Woo
• Louie Benjamin S

Classifications

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C16/0433 Primary

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/10

  Programming or data input circuits · CPC title