Method for integrated circuit patterning

Patent metadata

Field	Value
Publication number	US-9229326-B2
Application number	US-201414212708-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 14, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.

First claim

What is claimed is:

1. A method of forming a pattern for an integrated circuit (IC), the method comprising:
forming a first material layer over a substrate, wherein the first material layer has a first etch rate;
forming a resist layer over the first material layer;
exposing the resist layer to a radiation for patterning the resist layer, wherein the radiation reaches a first portion and a second portion of the first material layer, resulting in the first portion having a higher etch rate than the second portion;
developing the resist layer thereby forming a patterned resist layer, wherein the patterned resist layer includes a first opening and a second opening, the first opening exposes the first portion of the first material layer, and the second opening exposes the second portion of the first material layer; and
etching the first and second portions of the first material layer through the first and second openings, thereby forming a patterned first material layer.

2. The method of claim 1 , wherein the substrate includes a hard mask layer over which the first material layer is formed.

3. The method of claim 1 , wherein:
the first portion and the second portion each have a respective etch rate that is less than the first etch rate; and
the resist layer is a positive resist.

4. The method of claim 1 , wherein:
the first portion and the second portion each have a respective etch rate that is greater than the first etch rate; and
the resist layer is a negative resist.

5. The method of claim 1 , further comprising:
etching the substrate with the patterned first material layer as an etch mask.

6. The method of claim 1 , wherein the forming the first material layer includes a spin on coating process.

7. The method of claim 1 , wherein the substrate includes silicon.

8. The method of claim 1 , wherein the radiation is one of: a DUV ray, a EUV ray, an e-beam, an x-ray, and an ion beam.

9. The method of claim 1 , wherein the etching the first material layer includes a dry etching process.

10. The method of claim 1 , wherein the etching the first material layer includes an isotropic etching process.

11. The method of claim 1 , wherein the etching of the first and second portions of the first material layer forms third and fourth openings respectively in the first material layer, and wherein the third opening has a steeper sidewall than the fourth opening.

12. The method of claim 1 , wherein the first opening has a smaller dimension than the second opening.

13. A method of patterning a substrate, the method comprising the steps of:
forming a first layer over the substrate, wherein the first layer's etch rate is radiation-sensitive and has a first etch rate;
forming a positive resist layer over the first layer, wherein first and second portions of the positive resist layer are over first and second portions of the first layer respectively;
exposing the first and second portions of the positive resist layer to a radiation, wherein an etch rate of each of the first and second portions of the first layer becomes lower than the first etch rate as a result of the exposing, and wherein the first portion of the first layer has a higher etch rate than the second portion of the first layer;
developing the positive resist layer to remove the first and second portions of the positive resist layer;
etching the first and second portions of the first layer to expose the substrate; and
etching the substrate to form a pattern.

14. The method of claim 13 , wherein the substrate includes a hard mask layer over which the first layer is formed.

15. The method of claim 14 , wherein the hard mask layer includes one of: titanium nitride, silicon nitride, and titanium oxide.

16. The method of claim 13 , wherein the radiation has a wavelength less than 100 nanometer (nm).

17. A method of forming a pattern for an integrated circuit (IC), the method comprising:
forming a first layer over a substrate, wherein the first layer has a property that its etch rate increases when an energy dose of a radiation incident thereon increases;
forming a negative resist layer over the first layer;
exposing the negative resist layer to a radiation, wherein the radiation causes first and second portions of the first layer increase their respective etch rates, and wherein the first portion has a higher etch rate than the second portion;
patterning the negative resist layer thereby forming a patterned resist layer, wherein the patterned resist layer includes first and second openings, and wherein the first and second openings expose the first and second portions respectively; and
etching the first layer with the patterned resist layer as an etch mask.

18. The method of claim 17 , further comprising, before forming the first layer:
forming an anti-reflection coating layer over the substrate.

19. The method of claim 17 , further comprising:
etching the substrate with the etched first layer as an etch mask.

20. The method of claim 17 , wherein the etching of the first layer forms third and fourth openings in the first and second portions respectively, and wherein the third opening has a steeper sidewall than the fourth opening.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lu Yen-Cheng
• Chang Shu-Hao
• Yu Shinn-Sheng
• Wu Jui-Ching
• Chen Jeng-Horng
• Yen Anthony

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title