Device structure and methods of forming the same
US-2024371920-A1 · Nov 7, 2024 · US
Structure and method for tunable interconnect scheme
US9224643B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9224643-B2 |
| Application number | US-201113236264-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2011 |
| Priority date | Sep 19, 2011 |
| Publication date | Dec 29, 2015 |
| Grant date | Dec 29, 2015 |
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Abstract
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The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.
First claim
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What is claimed is: 1. A method, comprising: forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a first barrier layer of a first material in the plurality of vias and on the first dielectric material layer; forming a metal layer, contacting the first barrier layer, on the first dielectric layer and the substrate, wherein a portion of the metal layer fills the plurality of vias…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9224643B2 cover?
- The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching th…
- Who is the assignee on this patent?
- Lee Chung-Ju, Bao Tien-I, Yeh Ming-Shih, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/063. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).