All-tungsten scheme for source/drain contact, source/drain via, and gate via
US-2024395618-A1 · Nov 28, 2024 · US
Metal oxide semiconductor transistor and manufacturing method thereof
US8975672B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975672-B2 |
| Application number | US-201113292086-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 9, 2011 |
| Priority date | Nov 9, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
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The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor.
First claim
Opening claim text (preview).
What is claimed is: 1. A MOS transistor, comprising: a substrate; a gate dielectric layer disposed on the substrate; a gate disposed on the gate dielectric layer; a source/drain region disposed in the substrate at two sides of the gate, wherein the source/drain region has a part higher than a top surface of the substrate; and a silicide layer disposed on the part of the source/drain region which is higher than the top surface of the substrate, wherein the silicide layer co…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D64/0112Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8975672B2 cover?
- The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includ…
- Who is the assignee on this patent?
- Chiang Wen-Tai, Lin Chun-Hsien, United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D64/0112. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).