Forming conductive STI liners for FinFETS

Patent metadata

Field	Value
Publication number	US-9219115-B2
Application number	US-201314052328-A
Country	US
Kind code	B2
Filing date	Oct 11, 2013
Priority date	Oct 11, 2013
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

An integrated circuit device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor strip;
a semiconductor fin over the semiconductor strip;
a first dielectric layer and a second dielectric layer on opposite sidewalls of the semiconductor strip; and
a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielect…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Colinge Jean-Pierre

Classifications

• H10P14/416

  Electricity · mapped topic

• H10D64/01302

  Electricity · mapped topic

• H10W10/17

  Electricity · mapped topic

• H10W10/014

  Electricity · mapped topic

• H10D30/62 Primary

  Electricity · mapped topic