Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound

Patent metadata

Field	Value
Publication number	US-9219019-B2
Application number	US-201414215896-A
Country	US
Kind code	B2
Filing date	Mar 17, 2014
Priority date	Mar 17, 2014
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

First claim

We claim:

1. A semiconductor device package comprising:
a metallic Quad Flat No-Lead/Small Outline No-Lead QFN/SON-type leadframe having a pad and a plurality of elongated leads with solderable surfaces, at least one set of leads aligned in a row while having a solderable surface in a common plane;
a semiconductor device assembled on the pad and connected to the leads;
a package encapsulating the assembly and the leadframe, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and
grooves in the package material cut in the common-plane surface, the grooves extending along a portion of each lead length and exposing solderable lead surfaces, wherein the package material between adjacent grooves retains ridges having crests coplanar with the lead surfaces.

2. The package of claim 1 wherein the grooves extend from the package edge about half way along each lead length.

3. The package of claim 1 wherein the grooves are created by a material-removing method selected from a plurality including a pulsed laser-assisted micro-milling technique, an ablation technique, and a sputtering technique.

4. The package of claim 1 wherein the package is shaped as a hexahedron having sidewalls normal to the common plane.

5. The package of claim 4 wherein the row of aligned leads is positioned along a hexahedron edge formed by a package sidewall and the common plane.

Assignees

• Texas Instruments Inc

Inventors

• Lohia Alok Kumar
• Javier Reynaldo Corpuz
• Tran Andy Quang

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/438

  of side rails, e.g. having holes · CPC title