Method of integrated circuit fabrication

Patent metadata

Field	Value
Publication number	US-9219009-B2
Application number	US-201314136823-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

A method of fabricating an integrated circuit (IC) is disclosed. The method includes providing a substrate having a conductive feature. A dielectric layer is formed over the substrate, having an opening to expose the conductive feature. A tungsten (W) capping layer is formed over the conductive feature in the opening without using fluorine-containing gases. A bulk W layer is formed over the W capping layer.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit (IC), the method comprising:
providing a substrate having a conductive feature;
forming a dielectric layer having an opening over the substrate, wherein the opening aligns with the conductive feature and exposes at least a portion of the conductive feature;
forming a tungsten (W) capping layer over the conductive feature in the opening without using fluorine-containing gases; and
depositing a bulk W layer over the W capping layer.

2. The method of claim 1 , wherein the W capping layer is formed by metal-organic chemical vapor deposition (MOCVD) with a W organic precursor.

3. The method of claim 1 , wherein the W capping layer is formed by metal-organic chemical vapor deposition (MOCVD) with a W chloride precursor.

4. The method of claim 1 , wherein the conductive feature includes a semiconductor material.

5. The method of claim 4 , wherein prior to forming the W capping layer, a pre-silicide layer is formed over the conductive feature.

6. The method of claim 5 , wherein the forming the pre-silicide layer includes depositing a titanium layer over the conductive feature in the opening.

7. The method of claim 6 , wherein an anneal process is applied to the W capping layer and the conductive feature to form a silicide region in the conductive feature.

8. The method of claim 7 , wherein the anneal process is applied after the forming the W capping layer.

9. The method of claim 7 , wherein the anneal process is applied after the depositing the bulk W layer.

10. A method for fabricating an integrated circuit (IC), the method comprising:
providing a substrate having a conductive feature;
forming a dielectric layer having an opening over the substrate, wherein the opening aligns with the conductive feature and exposes at least a portion of the conductive feature;
depositing a pre-silicide metal layer over the conductive feature in the opening;
forming a non-fluorine-containing tungsten (W) capping layer over the pre-silicide metal layer in the opening;
depositing a bulk W layer over the W capping layer; and
after depositing the pre-silicide metal layer and the bulk W layer, annealing to form a silicide region in the conductive feature.

11. The method of claim 10 , wherein the non-fluorine-containing W capping layer is formed by metal-organic chemical vapor deposition (MOCVD) with a W organic precursor.

12. The method of claim 10 , wherein the non-fluorine-containing W capping layer is formed by MOCVD with metal-organic chemical vapor deposition (MOCVD) with a W chloride precursor.

13. The method of claim 10 , wherein the forming the pre-silicide layer includes depositing a titanium layer over the conductive feature in the opening.

14. The method of claim 10 , wherein the anneal process is applied after the forming the non-fluorine-containing W capping layer.

15. The method of claim 10 , wherein the anneal process is applied after the depositing the bulk W layer.

16. An integrated circuit (IC), comprising:
a substrate;
a conductive feature over the substrate;
a dielectric layer over the substrate, having an opening to expose at least a portion of the conductive feature;
a tungsten (W) capping layer formed by metal-organic chemical vapor deposition (MOCVD), over the conductive feature in the opening, including covering sidewalls of the opening; and
a bulk W layer over the W capping layer and filling in the opening, wherein a composition of W capping layer includes:
more than fifty atomic percent (50%) of W;
more than one atomic percent (1%) of carbon;
more than one atomic percent (1%) of oxygen;
more than one atomic percent (1%) of nitrogen; and
more than one atomic percent (1%) of hydrogen.

17. An integrated circuit (IC) comprising:
a substrate;
a conductive feature over the substrate;
a dielectric layer over the substrate, having an opening to expose at least a portion of the conductive feature;
a tungsten (W) capping layer formed by metal-organic chemical vapor deposition (MOCVD), over the conductive feature in the opening, including covering sidewalls of the opening; and
a bulk W layer over the W capping layer and filling in the opening, wherein a composition of chloride in the W capping layer is more than one atomic percent (1%).

18. The IC of claim 17 , further comprising:
a metal layer between the conductive feature and the W capping layer in the opening; and
a silicide region as a top portion of the conductive feature under the metal layer.

19. The IC of claim 18 , wherein the metal layer includes one or more materials from the group consisting of titanium (Ti), nickel (Ni), cobalt (Co), iron (Fe), molybdenum (Mo), tantalum (Ta), zirconium (Zr), hafnium (Hf), niobium (Nb), platinum (Pt), iridium (Ir), palladium (Pd), rhodium (Rh), ruthenium (Ru), lanthanides and their mixing.

20. The IC of claim 16 , further comprising a silicide feature disposed between the W capping layer and the conductive feature over the substrate.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lai Chia-Han
• Tsai Chun-I
• Lin Wei-Jung

Classifications

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title