Client voting-inclusive in-memory data grid (imdg) cache management
US-2016378666-A1 · Dec 29, 2016 · US
Data processing system with cache linefill buffer and method of operation
US9218293B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9218293-B2 |
| Application number | US-201314041910-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 30, 2013 |
| Priority date | Sep 30, 2013 |
| Publication date | Dec 22, 2015 |
| Grant date | Dec 22, 2015 |
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Abstract
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When data in first and second requests from a processor does not reside in cache memory, a first data element responsive to the second request is received by a cache controller from an external memory module after a first data element responsive to the first request and before the second data element responsive to the first request. Ownership of a linefill buffer is assigned to the first request when the first data element responsive to the first request is received. Ownership of the linefill buffer is re-assigned to the second request when the first data element responsive to the second request is received after the first data element responsive to the first request is received.
First claim
Opening claim text (preview).
What is claimed is: 1. A data processing system comprising: a central processing unit (CPU); an external memory module; a cache controller coupled to communicate with the CPU and the external memory unit, the cache controller including a linefill buffer; a cache memory module coupled to the cache controller, wherein the cache controller is configured to: when data in a first request and in a second request from the CPU does not reside in the cache memory module: request fi…
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- G06F12/0857Primary
Physics · mapped topic
- G06F12/0891Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9218293B2 cover?
- When data in first and second requests from a processor does not reside in cache memory, a first data element responsive to the second request is received by a cache controller from an external memory module after a first data element responsive to the first request and before the second data element responsive to the first request. Ownership of a linefill buffer is assigned to the first reques…
- Who is the assignee on this patent?
- Pho Quyen, Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0857. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 22 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).