Memory system and host device
US-2024394189-A1 · Nov 28, 2024 · US
US9286223B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9286223-B2 |
| Application number | US-201313864542-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 17, 2013 |
| Priority date | Apr 17, 2013 |
| Publication date | Mar 15, 2016 |
| Grant date | Mar 15, 2016 |
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Official abstract text for this publication.
A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.
Opening claim text (preview).
What is claimed: 1. A processor, comprising: a processing unit; a cache memory; a central request queue operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load reque…
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