Method for fabricating a strain feature in a gate spacer of a semiconductor device

Patent metadata

Field	Value
Publication number	US-9214552-B2
Application number	US-201414293206-A
Country	US
Kind code	B2
Filing date	Jun 2, 2014
Priority date	Nov 8, 2012
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

First claim

What is claimed is:

1. A method, comprising:
forming a gate stack over a substrate;
forming a spacer adjoining a sidewall of the gate stack;
forming a first recess in the substrate aligned to the spacer;
selectively etching a lower portion of the spacer relative to an upper portion of the spacer to form a second recess in the lower portion of the spacer; and
forming a strain feature in the second recess, wherein the step of selectively etching the lower portion of the spac…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Huang Yu-Lien

Classifications

• H10P50/642

  Electricity · mapped topic

• H10P14/40

  Electricity · mapped topic

• H10D64/691

  Electricity · mapped topic

• H10D64/018

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic