Via structure for three-dimensional circuit integration

Patent metadata

Field	Value
Publication number	US-9214435-B2
Application number	US-201213476056-A
Country	US
Kind code	B2
Filing date	May 21, 2012
Priority date	May 21, 2012
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.

First claim

What is claimed is:

1. A method for implementing three-dimensional integration (3Di) of functional components of a circuit comprising:
forming landing pads of upper and lower layers such that each of the landing pads includes a respective protective coating and such that a thickness of each protective coating is greater than the protective coating of any landing pad disposed on a lower layer in a stack and smaller than the protective layer of any landing pad disposed on a higher layer in the stack;
aligning an upper layer over an adjacent, lower layer during bonding of the upper and lower layers such that a landing pad disposed on the upper layer is offset from a landing pad disposed on the lower layer;
etching through the upper and lower layers to form a via hole in the layers and to expose the landing pads; and
filling the via hole with a conductive material to form a via that couples the landing pads of the upper and lower layers.

2. The method of claim 1 , wherein the aligning is iterated to form a stack of the layers such that an additional layer with a respective landing pad is added to the stack at each iteration of the aligning.

3. The method of claim 2 , wherein the aligning comprises aligning the landing pads of at least two of the layers in the stack such that the landing pads are successively offset in one direction.

4. The method of claim 2 , wherein the aligning comprises aligning each of the landing pads such that the landing pads are aligned in a spiral configuration.

5. The method of claim 2 , wherein the aligning comprises aligning each of the landing pads such that upper landing pads in the stack are aligned in a spiral configuration and the landing pad disposed on a bottom-most layer in the stack is disposed at the center of the spiral configuration.

6. The method of claim 1 , wherein cross-sectional areas of the landing pads of the upper and lower layers that are in contact with the conductive material are equal.

7. The method of claim 1 , wherein the etching etches the protective layers such that the protective layers are completely eroded simultaneously over at least a portion of each of the landing pads.

8. The method of claim 1 , wherein the via is a through-silicon via.

9. The method of claim 1 , wherein said etching comprises etching only a portion of the protective coating to expose a portion of the landing pads, leaving a remaining portion of the landing pads covered with the protective coating.

10. A method for implementing three-dimensional integration (3Di) of functional components of a circuit comprising:
aligning an upper layer over an adjacent, lower layer during bonding of the upper and lower layers such that a landing pad disposed on the upper layer is offset from a landing pad disposed on the lower layer and such that the landing pads are aligned in a spiral configuration;
etching through the upper and lower layers to form a via hole in the layers and to expose the landing pads; and
filling the via hole with a conductive material to form a via that couples the landing pads of the upper and lower layers.

11. The method of claim 10 , wherein the aligning is iterated to form a stack of the layers such that an additional layer with a respective landing pad is added to the stack at each iteration of the aligning.

12. The method of claim 11 , wherein the aligning comprises aligning the landing pads of at least two of the layers in the stack such that the landing pads are successively offset in one direction.

13. The method of claim 11 , wherein the aligning comprises aligning each of the landing pads such that upper landing pads in the stack are aligned in a spiral configuration and the landing pad disposed on a bottom-most layer in the stack is disposed at the center of the spiral configuration.

14. The method of claim 10 , wherein cross-sectional areas of the landing pads of the upper and lower layers that are in contact with the conductive material are equal.

15. The method of claim 10 , wherein the aligning and the bonding form a stack of the layers and wherein the method further comprises:
forming the landing pads of the upper and lower layers such that each of the landing pads includes a respective protective coating and such that thicknesses of the protective coatings progressively increase from the protective coating of the landing pad disposed on the layer at or adjacent to a bottom of the stack to the protective coating of the landing pad disposed on the layer at a top of the stack.

16. The method of claim 15 , wherein the etching etches the protective layers such that the protective layers are completely eroded simultaneously over at least a portion of each of the landing pads.

17. The method of claim 10 , wherein the via is a through-silicon via.

Assignees

• Farooq Mukta G
• Graves-Abe Troy L
• Skordas Spyridon
• Winstel Kevin R
• Globalfoundries Inc

Inventors

• Farooq Mukta G
• Graves-Abe Troy L
• Skordas Spyridon
• Winstel Kevin R

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W80/732

  having shape changed during the connecting · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title