Conflict detection for self-aligned multiple patterning compliance

Patent metadata

Field	Value
Publication number	US-9213790-B2
Application number	US-201414326553-A
Country	US
Kind code	B2
Filing date	Jul 9, 2014
Priority date	Jan 23, 2013
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

First claim

What is claimed is:

1. A method for performing design layout, comprising:
receiving an initial design layout associated with an electrical component;
generating an initial representation of the initial design layout, the initial representation comprising one or more nodes connected by one or more edges, a node representing a polygon within the initial design layout and wherein:
a same-process edge of the one or more edges connects a first node generated by a first pattern process and a second node generated by the first pattern process, and
a different-process edge of the one or more edges connects a third node generated by the first pattern process and a fourth node generated by a second pattern process;

utilizing a merge technique to generate a cluster graph from the initial representation, wherein the same-process edge is not visible in the cluster graph and the different-process edge is visible in the cluster graph; and
identifying a conflict associated with the initial design layout based upon the cluster graph, wherein the method is implemented by a processing unit that executes processor-executable instructions stored on a non-transitory computer-readable medium.

2. The method of claim 1 , the merge technique comprising:
merging the first node with the second node to generate a first node cluster of the cluster graph.

3. The method of claim 2 , the identifying a conflict comprising:
identifying the conflict based upon a loop within the cluster graph comprising an odd number of node clusters.

4. The method of claim 3 , wherein a segment of the loop corresponds to the different-process edge.

5. The method of claim 2 , the merge technique comprising:
merging the third node with the first node and the second node to generate the first node cluster when at least one of the first node or the second node is connected to the third node by a second same-process edge.

6. The method of claim 1 , the generating an initial representation comprising at least one of:
connecting the third node to the fourth node using the different-process edge based upon a space between a third polygon, represented by the third node, and a fourth polygon, represented by the fourth node, corresponding to a first spacing threshold range; or
connecting the first node to the second node using the same-process edge based upon a space between a first polygon, represented by the first node, and a second polygon, represented by the second node, corresponding to a second spacing threshold range.

7. The method of claim 1 , comprising:
responsive to a modification of the initial design layout to resolve the conflict, generating a design layout based upon the modified initial design layout;
generating one or more mandrel pattern layers for the design layout, a mandrel pattern layer comprising mandrel surrounded at least in part by spacer; and
generating one or more trim pattern layers for the design layout.

8. A method for performing design layout, comprising:
receiving an initial design layout associated with an electrical component;
generating an initial representation of the initial design layout, the initial representation comprising:
a first node representing a first polygon of the initial design layout;
a second node representing a second polygon of the initial design layout, the second node connected to the first node by a same-process edge; and
a third node representing a third polygon of the initial design layout, the third node connected to the second node by a different-process edge;

utilizing a merge technique to generate a cluster graph from the initial representation, the cluster graph comprising:
a first node cluster representing the first node and the second node; and

identifying a conflict associated with the initial design layout based upon the cluster graph, wherein the method is implemented by a processing unit that executes processor-executable instructions stored on a non-transitory computer-readable medium.

9. The method of claim 8 , the cluster graph comprising a second node cluster representing the third node when the third node is connected to the first node by a second different-process edge.

10. The method of claim 9 , the second node cluster connected to the first node cluster by at least one of the different-process edge or the second different-process edge.

11. The method of claim 8 , the first node cluster representing the third node when the third node is connected to the first node by a second same-process edge.

12. The method of claim 8 , the cluster graph comprising a loop, the loop formed by the first node cluster and the different-process edge.

13. The method of claim 12 , the identifying a conflict comprising:
identifying the conflict based upon the loop comprising an odd number of node clusters.

14. The method of claim 8 , comprising:
displaying the conflict within a visualization of the initial design layout.

15. The method of claim 14 , the displaying comprising:
providing a spacing constraint recommendation for the conflict.

16. The method of claim 8 , comprising:
modifying the initial design layout to resolve the conflict and to generate a modified initial design layout.

17. The method of claim 16 , the modifying the initial design layout comprising:
applying at least one of a min space rule, an island rule, an isolated trench rule, a corner-to-corner rule, or a flip assignment rule to the initial design layout.

18. A system for performing design layout, comprising:
a processing unit; and
a non-transitory computer-readable medium for storing processor-executable instructions that when executed by the processing unit perform operations, the operations comprising:
receiving an initial design layout associated with an electrical component;
generating an initial representation of the initial design layout, the initial representation comprising one or more nodes connected by one or more edges, a node representing a polygon within the initial design layout and wherein:
a same-process edge of the one or more edges connects a first node generated by a first pattern process and a second node generated by the first pattern process, and
a different-process edge of the one or more edges connects a third node generated by the first pattern process and a fourth node generated by a second pattern process;

utilizing a merge technique to generate a cluster graph from the initial representation, wherein the same-process edge is not visible in the cluster graph and the different-process edge is visible in the cluster graph; and
identifying a conflict associated with the initial design layout based upon the cluster graph.

19. The system of claim 18 , wherein the merge technique comprises merging the first node with the second node to generate a first node cluster of the cluster graph.

20. The system of claim 19 , the operations comprising identifying the conflict based upon a loop, formed by at least the first node cluster and the different-process edge, comprising an odd number of node clusters.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hsu Chin-Chang
• Lin Hunglung
• Shen Ying-Yu
• YANG Wen-ju
• Hsieh Ken-Hsien

Classifications

• G03F7/70466

  Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F7/70475

  Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display · CPC title

• G06F17/5081

  Physics · mapped topic