Adaptive data re-compaction after post-write read verification operations

Patent metadata

Field	Value
Publication number	US-9213601-B2
Application number	US-201314095881-A
Country	US
Kind code	B2
Filing date	Dec 3, 2013
Priority date	Dec 3, 2013
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

Approaches are presented for adaptively re-compacting data when errors are found during a post-write verify in a non-volatile memory system, such as flash NAND memory. In one example, user data along with corresponding parity data is written into a block of non-volatile memory. After writing in the user data, but prior to writing the corresponding parity data, the user data is checked. For any word lines that fail this post-write verify, the parity data for the block is adjusted to remove the contribution of any failed word lines before this modified parity data is written into the block. The data corresponding to the failed word lines can then be written elsewhere in the memory system.

First claim

It is claimed:

1. A method of operating a non-volatile memory system including one or more non-volatile memory circuits each having one or more arrays of non-volatile memory cells formed along word lines as a plurality of erase blocks, each erase block corresponding to a plurality of word lines, the method comprising:
storing a first plurality of pages of data in a first section of the non-volatile memory system;
subsequently programing the first plurality of pages from the fir…

Assignees

• Sandisk Technologies Inc

Inventors

• Tuers Daniel
• Ta Thomas
• Manohar Abhijeet

Classifications

• G06F11/1072 Primary

  Physics · mapped topic

• G06F11/1068 Primary

  Physics · mapped topic