Interface for controlling the phase alignment of clock signals for a recipient device

Patent metadata

Field	Value
Publication number	US-9213359-B2
Application number	US-201213726383-A
Country	US
Kind code	B2
Filing date	Dec 24, 2012
Priority date	Dec 24, 2012
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronizing circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronizing circuits. A further synchronizing circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration.

First claim

We claim:

1. Interface circuitry for transmitting transactions between an initiator and a recipient, said interface circuitry comprising:
a clock input for receiving a clock signal;
at least one transaction input for receiving transactions;
at least one clock output for outputting said clock signal;
a first clock path for transmitting said clock signal from said clock input to said clock output;
at least one transaction output for outputting said transactions to said rec…

Assignees

• Advanced Risc Mach Ltd

Inventors

• Prakash Gyan
• Kumar Nidhir

Classifications

• G06F1/10

  Physics · mapped topic

• G06F1/12 Primary

  Physics · mapped topic