Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-9209811-B2
Application number	US-201414461163-A
Country	US
Kind code	B2
Filing date	Aug 15, 2014
Priority date	Oct 18, 2011
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

First claim

What is claimed is:

1. A semiconductor integrated circuit device, comprising:
a core region in which core logic circuit is arranged; and
a plurality of I/O cells arranged in a first direction, each of the plurality of I/O cells comprising
a bonding pad,
an I/O logic circuit, and
an I/O buffer circuit,
wherein an I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged are disposed under the bonding pad in plan view, and
wherein the I/O logic region and the I/O buffer region are arranged side by side in the first direction.

2. The semiconductor integrated circuit device according to claim 1 , wherein
a deep N-well included in the I/O logic region and a deep N-well included in the I/O buffer region are separated from each other.

3. The semiconductor integrated circuit device according to claim 1 , wherein
the I/O logic circuit and the I/O buffer circuit share a first wiring supplying a first voltage and a second wiring supplying a second voltage.

4. The semiconductor integrated circuit device according to claim 2 , wherein
the I/O logic circuit and the I/O buffer circuit share a first wiring supplying a first voltage and a second wiring supplying a second voltage.

5. The semiconductor integrated circuit device according to claim 3 , wherein
the first voltage and the second voltage are a power supply voltage and a ground voltage, respectively, for the I/O buffer circuit and the I/O logic circuit.

6. The semiconductor integrated circuit device according to claim 3 ,
wherein each of the plurality of I/O buffer circuit includes a level shifter circuit, a P buffer and an N buffer, and
wherein a P buffer region in which the P buffer is arranged is arranged beside a level shifter region in which the level shifter circuit is arranged.

7. The semiconductor integrated circuit device according to claim 3 , wherein
the I/O buffer region comprises a PMOS transistor, an NMOS transistor, first and second resistive elements, and first and second diode elements,
the PMOS transistor has a gate terminal connected to the IO logic circuit, one of a source terminal and a drain terminal connected to a back-gate terminal and the first wiring, and the other one of the terminals connected to a first terminal of the first resistive element,
the first resistive element has a second terminal connected to the pad,
the first diode element is connected between the first wiring and the pad,
the NMOS transistor has a gate terminal connected to the IO logic circuit, one of a source terminal and a drain terminal is connected to a back-gate terminal and the second wiring, and the other one of the terminals is connected to a first terminal of the second resistive element,
the second resistive element has a second terminal connected to the pad, and
the second diode element is connected between the second wiring and the pad.

8. The semiconductor integrated circuit device according to claim 1 ,
wherein each of the plurality of I/O cells includes a level shifter circuit;
wherein the level shifter region in which the level shifter circuit is arranged includes:
a first voltage region in which a circuit supplying a first power supply voltage to the I/O logic circuit is arranged; and
a second voltage region in which a circuit supplying a second power supply voltage to the core logic circuit is arranged, and
wherein the first voltage region is arranged within the I/O logic region, and
the second voltage region is arranged between the core region and a pair of the I/O logic region and the I/O buffer region.

Assignees

• Renesas Electronics Corp

Inventors

• Sakamoto Kazuo
• Morino Naozumi
• Tanaka Kazuo
• Ishizuka Hiroyasu

Classifications

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

• H03K19/08 Primary

  using semiconductor devices (H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12) · CPC title

• H10D84/975

  Wiring regions or routing · CPC title