Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits

Patent metadata

Field	Value
Publication number	US-9209137-B2
Application number	US-201414333348-A
Country	US
Kind code	B2
Filing date	Jul 16, 2014
Priority date	Aug 3, 2012
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

First claim

What is claimed is:

1. An electronic circuit design for flexible packaging, comprising:
a plurality of integrated circuit blocks, wherein each integrated circuit block is configured to be operable as an individual integrated circuit block and in parallel with at least one other of the integrated circuit blocks;
seal-rings including an outer seal-ring and inner seal-rings, the outer seal-ring disposed about the periphery of the plurality of integrated circuit blocks and the inner seal-ring portions surrounding individual integrated circuit blocks; and
the integrated circuit blocks spaced apart from each other by at least a minimum die cutting distance.

2. The electronic circuit design of claim 1 , wherein there is at least one inner seal-ring surrounding each integrated circuit block.

3. The electronic circuit design of claim 2 , wherein the outer seal-ring is separate and distinct from each inner seal-ring.

4. The electronic circuit design of claim 1 , wherein each integrated circuit block is a system-on-a-chip.

5. An electronic circuit package, comprising:
a plurality of integrated circuit blocks;
a first seal ring surrounding a first of the integrated circuit blocks;
a second seal ring surrounding a second of the integrated circuit blocks; and
a third seal ring surrounding the first and the second integrated circuit blocks,
wherein the first and second seal rings are operable to provide the first and second integrated circuit blocks as individual circuit blocks after die cutting, and
wherein the third seal ring is operable to provide the first and second integrated circuit blocks as a single parallel circuit block after die cutting.

6. The electronic circuit package of claim 5 , wherein:
the first seal ring further surrounds a third of the integrated circuit blocks.

7. The electronic circuit package of claim 5 , wherein:
the seal rings are rectangularly shaped with scalloped corners.

8. The electronic circuit package of claim 5 , wherein:
the first and the second integrated circuit blocks are communicatively coupled to each other via signal interconnections that cross the first and second seal rings.

Assignees

• Avago Technologies General Ip
• Avago Technologies General Ip

Inventors

• Vu Duc Anh
• Pragasam Jayalakshmana Kumar
• Meduri Vijay
• Attaran Seyed
• Grubisich Michael J
• Ahmed Syed
• Singh Aniket

Classifications

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W76/60

  Seals · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title