Test apparatus and test module

Patent metadata

Field	Value
Publication number	US-9201750-B2
Application number	US-201213430694-A
Country	US
Kind code	B2
Filing date	Mar 27, 2012
Priority date	Mar 1, 2012
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

Provided is a test apparatus that tests a device under test, comprising a test module that communicates with the device under test to test the device under test; and a control apparatus that executes a plurality of test programs, causes the test module to perform tests corresponding respectively to the test programs, receives test results from the test module, and performs predetermined result processes on the test results. The control apparatus stores an execution order of the test programs, and executes at least a portion of the result processes in an order indicated by the stored execution order.

First claim

What is claimed is:

1. A test apparatus that tests a device under test, comprising:
a test module that communicates with the device under test to test the device under test; and
a control apparatus that executes a first test program and a second test program, stores an execution order of the first test program and the second test program, causes the test module to perform a first test and a second test corresponding respectively to the first test program and the second test program, receives a first test result corresponding to the first test and a second test result corresponding to the second test from the test module, and performs result processes on the first test result and the second test result in parallel such that, among the result processes, a predetermined result process common to the first test result and the second test result is performed on the first test result and the second test result in an order indicated by the stored execution order, wherein
the test module includes a first memory and a second memory that store the first test result and the second test result, and
the test module performs the first test and the second test such that at least a portion of a result processing time period of the first test, which is from when the first test result stored in the first memory begins to be transmitted to the control apparatus to when performance of the result processes on the first test result by the control apparatus is finished, overlaps with at least a portion of a test execution time period of the second test, which is from when the second test is begun to when the second test result is stored in the second memory.

2. The test apparatus according to claim 1 , wherein
the test module starts to perform the second test using the second memory at a timing at which a test execution time period of the first test using the first memory is finished, the test execution time period of the first test being from when the first test is begun to when the first test result is stored in the first memory.

3. The test apparatus according to claim 2 , wherein
the test module starts to perform the second test using the second memory in parallel with starting transmission of the first test result stored in the first memory to the control apparatus.

4. The test apparatus according to claim 1 , wherein
the test module stores test results corresponding to sequentially executed test programs alternately between the first memory and the second memory for each test program.

5. A test apparatus that tests a device under test, comprising:
a test module that communicates with the device under test to test the device under test; and
a control apparatus that executes a first test program and a second test program, stores an execution order of the first test program and the second test program, causes the test module to perform a first test and a second test corresponding respectively to the first test program and the second test program, receives a first test result corresponding to the first test and a second test result corresponding to the second test from the test module, and performs result processes on the first test result and the second test result in parallel such that, among the result processes, a predetermined result process common to the first test result and the second test result is performed on the first test result and the second test result in an order indicated by the stored execution order, wherein
when a result process performed on the second test result immediately prior to the predetermined process ends before the predetermined process is performed on the first test result, the control apparatus postpones performance of the predetermined process on the second test result until the predetermined process is performed on the first test result.

6. The test apparatus according to claim 5 , wherein
the predetermined result process is a final process, which is performed last among the result processes performed on the first test result and performed last among the result processes performed on the second test result.

7. The test apparatus according to claim 6 , wherein
the final process is a process to classify the device under test according to the test results.

8. A control apparatus for use in a test apparatus that tests a device under test and includes a test module that communicates with the device under test to test the device under test, the control apparatus comprising:
a memory for storing an execution order of a first test program and a second test program, wherein
the control apparatus executes the first test program and the second test program, stores the execution order of the first test program and the second test program, causes the test module to perform a first test and a second test corresponding respectively to the first test program and the second test program, receives a first test result corresponding to the first test and a second test result corresponding to the second test from the test module, and performs result processes on the first test result and the second test result in parallel such that, among the result processes, a predetermined result process common to the first test result and the second test result is performed on the first test result and the second test result in an order indicated by the stored execution, and
when a result process performed on the second test result immediately prior to the predetermined process ends before the predetermined process is performed on the first test result, the control apparatus postpones performance of the predetermined process on the second test result until the predetermined process is performed on the first test result.

Assignees

• Sugimura Hajime
• Yaguchi Takeshi
• Nakajima Takahiro
• Advantest Corp

Inventors

• Sugimura Hajime
• Yaguchi Takeshi
• Nakajima Takahiro

Classifications

• G06F11/26

  Functional testing · CPC title

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title