Suppressing dielectric absorption effects in sample-and-hold systems

Patent metadata

Field	Value
Publication number	US-9197235-B2
Application number	US-201414472160-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Apr 14, 2014
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.

First claim

What is claimed is:

1. Sample-and-hold (S/H) circuitry operating in track and hold phases, and comprising:
a first S/H circuit having a first hold capacitor at which a first voltage value is maintained in the hold phase, and
a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase,
the DA-suppressing circuit being configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value which is negatively correlated with the first voltage value.

2. The S/H circuitry of claim 1 , wherein the DA-suppressing circuit includes:
an inverting amplifier having a first input responsive to the first voltage value and an output, and
a first switching element for coupling the output of the inverting amplifier to the first holding capacitor after the hold phase so as to operate the S/H circuitry in the additional phase.

3. The S/H circuitry of claim 2 , wherein the inverting amplifier has a second input supplied with a bias voltage value.

4. The S/H circuitry of claim 3 , wherein the DA-suppressing circuit further includes a second S/H circuit having an input coupled to an output of the first S/H circuit and an output coupled to the first input of the inverting amplifier.

5. The S/H circuitry of claim 4 , wherein the second S/H circuit includes a second hold capacitor and a second switching element for coupling the second hold capacitor to the output of the first S/H circuit during the hold phase.

6. The S/H circuitry of claim 5 , wherein the second switching element is opened before a transition from the hold phase to the additional phase so as maintain the first voltage value at the second holding capacitor.

7. The S/H circuitry of claim 6 , wherein the first switching element is opened and the second switching element is closed to switch the S/H circuitry from the additional phase to the track phase.

8. A sampling analog-to-digital converter operating in acquisition and conversion phases and comprising:
an array of capacitors,
an array of switches controllable to couple the capacitors of the array to sources of at least two different voltages during the conversion phase, applying a first average voltage value across the capacitors, and
a dielectric absorbtion (DA)-suppressing circuit for controlling the array of switches during an additional phase after completing the conversion phase and before entering the acquisition phase,
the DA-suppressing circuit being configured to control the switches to apply a second average voltage value across the capacitors, the second average voltage value being negatively correlated with the first average voltage value.

9. The converter of claim 8 , wherein the DA-suppressing circuit has a first input responsive to multiple first control signals produced by the converter, and an output for producing multiple second control signals corresponding to the respective first control signals and supplied to the respective switches of the array to control the switches so as to apply the second average voltage value across the capacitors.

10. The converter of claim 9 , wherein the DA-suppressing circuit further has a second input supplied with an enable signal asserted at a first logic level during the acquisition and conversion phases, and asserted at a second logic level during the additional phase.

11. The converter of claim 10 , wherein the DA-suppressing circuit is configured to produce the second control signals having values substantially equivalent to values of the respective first control signals when the enable signal is at the first logic level, and to produce the second control signals having values logically inverted with respect to the values of the corresponding first control signals when the enable signal is at the second logic level.

12. The converter of claim 11 , wherein the DA-suppressing circuit further includes multiple latches having inputs responsive to the respective first control signals.

13. The converter of claim 12 , wherein the DA-suppressing circuit includes multiple exclusive OR gates having first inputs coupled to the outputs of the respective latches, second inputs responsive to the enable signal, and outputs for producing the respective second control signals.

Assignees

• Linear Techn Inc

Inventors

• Thomas Andrew Joseph

Classifications

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• G11C27/026

  associated with an amplifier (G11C27/028 takes precedence) · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title