Semiconductor die, semiconductor package and substrate dicing method
US-2024421000-A1 · Dec 19, 2024 · US
Scribe line structure for wafer dicing and method of making the same
US9190359B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9190359-B2 |
| Application number | US-201314077225-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 12, 2013 |
| Priority date | May 13, 2008 |
| Publication date | Nov 17, 2015 |
| Grant date | Nov 17, 2015 |
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Abstract
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A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path.
First claim
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What is claimed is: 1. A scribe line structure between die regions, comprising: a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the…
Assignees
Inventors
Classifications
- H10P54/00Primary
Electricity · mapped topic
Electricity · mapped topic
- H10W46/00Primary
Electricity · mapped topic
Electricity · mapped topic
- H01L23/544Primary
Electricity · mapped topic
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- What does patent US9190359B2 cover?
- A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing p…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).